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Keyon Jie d58b35c4e7 ssp: switch to use SCR for BCLK generation. 
switch the BCLK generation from shim ssp clock divider to
using SSCR0.SCR, as the divider may lead to jitter.

clear and remove M/N divider part code.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
 		2016-12-22 16:18:36 +00:00
src ssp: switch to use SCR for BCLK generation. 2016-12-22 16:18:36 +00:00
.gitignore core: initial import of open source DSP firmware 2016-09-22 16:02:43 +01:00
LICENCE core: initial import of open source DSP firmware 2016-09-22 16:02:43 +01:00
Makefile.am build: fix configure naming to use newlib header directory. 2016-10-18 17:18:16 +01:00
README readme: Fix DSP compiler tool directy setting for platform build 2016-10-31 23:31:05 +00:00
autogen.sh core: initial import of open source DSP firmware 2016-09-22 16:02:43 +01:00
build-all.sh build: fix configure naming to use newlib header directory. 2016-10-18 17:18:16 +01:00
configure.ac core: Add dsp-core option for XTENSA compiler 2016-11-02 16:11:26 +00:00
git-version-gen core: initial import of open source DSP firmware 2016-09-22 16:02:43 +01:00

README 

Build Instructions

1) Run "autogen.sh" 

2) Run the following configure based on your platform.

Baytrail :-

./configure --with-arch=xtensa --with-platform=baytrail --with-root-dir=~/source/reef/xtensa-byt-elf --host=xtensa-byt-elf host_alias=xtensa-byt-elf

Cherrytrail :-

./configure --with-arch=xtensa --with-platform=cherrytrail --with-root-dir=~/source/reef/xtensa-byt-elf --host=xtensa-byt-elf host_alias=xtensa-byt-elf

3) make

4) make bin