Commit Graph

9359 Commits

Author SHA1 Message Date
Ranjani Sridharan 6e7f31c141 module_adapter: Add a no_pause field for modules
Add a new field, no_pause in struct processing_module which will be set
by modules that do not support pause, ex: mixer.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
2022-12-15 20:44:20 +02:00
Ranjani Sridharan af352a2bb2 module_adapter: Add the verify_params_flags field for modules
Add a verify_params_flags field in struct processing_module which should
be set by the modules during initialization to indicate which
parameters should be skipped during comp_verify_params().

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
2022-12-15 20:44:20 +02:00
Kai Vehmanen 543acc124d .github/workflows: add tgl-h IPC4 build
Add build check for Intel 'tgl-h' IPC4 build.

Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-12-15 09:09:03 -08:00
Tinghan Shen c916f3fdd7 src: mediatek: Fix MediaTek company name and SPDX checkpatch warnings
The company name should be MediaTek instead of Mediatek.
                                ^                   ^

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen f28dc601cb platform: Add mt8188 to Kconfig
Add mt8188 to Kconfig.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen 4139ca8fe4 platform: Add build support for MediaTek mt8188 platform
Add CMakefile for MediaTek mt8188 platform to build it.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen 3b8e2e4113 config: Add default config for mt8188
Add default config for mt8188 platform.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen cd8e75df5d platform: mtk: Add support for mt8188 platform
mt8188 platform integrates a single-core HIFI5 DSP.

The highest DSP operation frequency is 800MHz which requires
0.75v working voltage. otherwise, it should switch to 26M which
can operate at the lowest working voltage 0.55v.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen bff918a271 drivers: mtk: Reuse mt8186 drivers for mt8188
Reuse mt8186 interrupt, timer, and ipc drivers for mt8188.
mt8188 DSP has 32 interrupts, 4 internal timers, and 5 mailbox for IPC.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen 02cf74ae21 platform: mtk: add mt8188 memory layout and register definitions
Add memory layout and register address for mtk mt8188.

[Cache]
I-Cache: 64KB, 4-way Associativity
D-Cache: 128KB, 4-way Associativity

[Memory]
DRAM: DSP can access DRAM shared with CPU
L2TCM: 512KB DSP SRAM POOL

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Tinghan Shen 5fe6aa2a51 platform: mtk: add xtensa headers for mt8188
Add xtensa headers for mtk mt8188 platform.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2022-12-15 16:11:23 +00:00
Guennadi Liakhovetski c426f810cb module-adapter: attach and detach buffers correctly
When attaching multiple buffers via their uncached list heads, we
have to make sure to synchronise cache of adjacent buffers.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-12-15 12:25:30 +00:00
Guennadi Liakhovetski a95ea9bfb1 buffer: move linking and unlinking code to functions
We want to re-use the code, used to synchronise caches when linking
and unlinking buffers, move it to two new functions.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-12-15 12:25:30 +00:00
barry.jan 6275d18ce2 module_adapter: free memory resource
Since module-specific prepare API will be called every time on prepare
 of module_adapter (stream start trigger), the reset API should
free all memory that was allocated during the prepare API.

Signed-off-by: barry.jan <barry.jan@waves.com>
2022-12-15 12:23:48 +00:00
Yong Zhi 2cfa90d324 topology2: cavs-rt5682: add deep buffer support on headset
Deep buffer is mixed with ssp0 stream.
Override mixout copier audio_format.1 from 32/24 to 32/32 for I2S.

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
2022-12-15 12:23:00 +00:00
Marc Herbert 501204c684 xtensa-build-zephyr.py: objcopy --remove-section .comment zephyr.strip
Make stripped ELF files compiled by XCC identical across different
machines.

Some Xtensa compilers (ab?)use the .ident / .comment
section and append the typically absolute and not
reproducible /path/to/the.c file after the usual
compiler ID.

https://sourceware.org/binutils/docs/as/Ident.html

strip --strip-all does not remove the .comment section.
Remove ourselves like some gcc test scripts do:

 https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c7046906c3ae

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-15 13:55:07 +02:00
Kai Vehmanen dba643cf2b west.yml: upgrade Zephyr to c5b270e7b003
Total of 440 commits, including following related to
intel_adsp/sparse/dmic/xtensa:

603cc2704579 dma: Add max block count attribute
2c162449eb4c xtensa: linker: Fix #52539 by updating the linker scripts
2dd4cbc75592 dts: xtensa: intel: update cavs25_tgph to match cavs25

Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-12-15 12:36:03 +02:00
Ievgen Ganakov 20e39758f0 module_adapter: fix large blob processing
Use correct IPC4 mailbox size. Correct
calculation of fragment_size.

Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
2022-12-15 12:35:20 +02:00
Kwasowiec, Fabiola 18dc72fa89 comp: fix bind order
Current ipc_comp_connect() connects the source first, then calls comp_bind
and only then connects the sink. This leads to errors with modules that
assume sink to be connected at bind. This is a valid assumption, so fix
the order in ipc_comp_connect().

Signed-off-by: Kwasowiec, Fabiola <fabiola.kwasowiec@intel.com>
2022-12-15 09:09:19 +01:00
Bard Liao 99a65fc7d7 topology2: cavs-sdw: fix DEEP_BUFFER_PIPELINE_SINK
mixout-gain-dai-copier-playback.2 pipeline id has been changed to 1.
Need to change mixout.2.1 to mixout.1.1 as well.

Fixes: f0a010052b ("topology2: cavs-sdw: group route and pipeline index")
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
2022-12-14 17:03:45 +00:00
Serhiy Katsyuba 0ecfc78139 ipc4: fix crash when using ALH DAI
dma_buffer is not yet created when ipc_dai_data_config() is called.
Accessing dma_buffer->stream leads to crash.

Anyway, there is no need to set
dd->dma_buffer->stream.frame_fmt = SOF_IPC_FRAME_S32_LE
as this is done just after ipc_dai_data_config() in dai_params()
by calling buffer_set_params().

Somewhat similar fix for IPC3 was done some time ago: 0ba90d8e2a.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2022-12-14 14:59:28 +00:00
Chunxu Li b0ae15a0bc topology1: mt8186: support 1ms pipeline capture period
Default support 1ms period capture pipeline to update host
position more precisely.

Signed-off-by: Chunxu Li <chunxu.li@mediatek.com>
2022-12-14 14:37:49 +00:00
Guennadi Liakhovetski 0af54f9fbc buffer: handle prefetch
Data cache on Xtensa can be prefetched speculatively. In a sequence:

modify cached
modify uncached
modify cached

it isn't enough to writeback-invalidate caches after the first line.
Cache can be prefetched immediately before the second like,
preserving an outdated version of the data and then using it in line
3. The correct sequence is:

modify cached
writeback cache
modify uncached
invalidate cache
modify cached

Adjust buffer linking and unlinking accordingly.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-12-14 14:26:40 +00:00
Guennadi Liakhovetski 007247cee8 coherent: align object allocation size to a cache line
Objects, used with the coherent API must be allocated to align to a
cache line boundary at the end. Since heap allocations always begin
on a cache line boundary, we just need to align the size to an
integer number of cache line sizes. Otherwise the header from the
next heap allocation can reside in the same cache line and therefore
be overwritten with stale data.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-12-14 14:26:40 +00:00
Curtis Malainey 74fd291499 audio: google: Fix AEC mock
Some build errors that appear to be missed in xcc but gcc catches

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
2022-12-14 14:10:05 +00:00
Curtis Malainey 9e7353a5bb audio: google: Add missing return check
Check those errors

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
2022-12-14 14:10:05 +00:00
Curtis Malainey 0c5ddaf617 audio: google: fix include for aec mock
missed rtos specific header swap

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
2022-12-14 14:10:05 +00:00
Kalva, DineshKumar 86203383a6 platform:amd:enable acp SRAM
Configure ACP sram access.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
2022-12-14 14:04:30 +00:00
Kalva, DineshKumar a992de9a05 drivers: amd: enable acp SRAM
Configure ACP sram access.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
2022-12-14 14:04:30 +00:00
Pierre-Louis Bossart c91326bda2 topology1: add ADL Rooks County laptop LAPRC710
Amplifier is on link 2, not 3, in this platform

Fixes: https://github.com/thesofproject/linux/issues/4088
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2022-12-14 13:59:56 +00:00
Paul Olaru 80a60ceac2 module_adapter: cadence: Treat nonfatal errors as nonfatal
The processing function can at times return a nonfatal error.
Such errors should not be treated as hard errors.

This commit changes it so that they are instead treated as a warning.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2022-12-14 13:30:17 +00:00
Tomasz Leman cd2349834c config: mtl: enabling power domains
Enabling power domains on meteorlake.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-14 11:43:34 +01:00
Tomasz Leman cf2a487048 config: mtl: pm settings cleanup
Grouping all zephyr power management setting together.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-14 11:43:34 +01:00
Curtis Malainey 73f6171bb3 audio: move google components to a subfolder
just some minor house cleaning

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
2022-12-13 12:29:29 -08:00
Przemyslaw Blaszkowski 0664718a58 ipc4: only primary core sends ipc to host
Remove option to immediately send IPC in ipc_send_msg().

In current implementation, secondary core can directly write IPC mailbox
and registers. It may lead to conflict with IPC's that are being send
from queue on primary core.

All IPC responses and notifications should be queued on primary core to
synchronize two types of DSP to host messages between cores.

Changing flow only for IPC4/Zephyr. Leaving XTOS path unchanged.

Signed-off-by: Przemyslaw Blaszkowski <przemyslaw.blaszkowski@intel.com>
2022-12-12 12:11:46 +00:00
Marc Herbert 6516f907aa sparse: pass platform argument to error filter script
So we can make adjust the warnings based on the platform.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-12 12:05:26 +00:00
Marc Herbert e39205cc11 parse_sparse_output.sh: new sparse_errors array
Zero functional change, pure preparation for the next commit.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-12 12:05:26 +00:00
Marc Herbert 2aa9527d0a .github/sparse: use --pristine
--pristine makes no difference for github but it's a good for anyone
trying to reproduce results and copying the command.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-12 12:05:26 +00:00
Per Åhgren e616b4210b Updating of GoogleRtcAudioProcessing component to provide a more general behavior
Changes in the GoogleRtcAudioProcessing component to
--Allow sample rate and number of channels to explicitly be specified.
--Update the memory management.
--Allow parameters to be passed.
--Allow more than mono to be processed
--Allow parameters to be specified from Kconfig

Signed-off-by: Per Åhgren <peah@google.com>
2022-12-09 16:00:16 -08:00
Pin-chih Lin 6d80a5565b src: avoid restless warn messages from comp_get_data_blob()
At present codes of rtnr and google-rtc-audio-processing, a
reconfigure() function is called per copy() routine to dynamically
update config blob in COMP_STATE_ACTIVE state. The logic has no
problem in practice.

However, if there are cases that config blob is always empty or
arrived late, hundreds of warning message lines per second will be
produced by comp_get_data_blob() called from reconfigure(),
restlessly complaining that data blob is not set.

This commit adds a pre-check for early-return under such cases to skip
comp_get_data_blob() calls with warn messages.

Signed-off-by: Pin-chih Lin <johnylin@googele.com>
2022-12-09 16:59:05 +00:00
Pin-chih Lin e9dfeab7af memory: intel: increase task stack size for specific modules
Larger stack context stack size is required for RTNR and
GOOGLE_RTC_AUDIO integration on Intel platforms.

Signed-off-by: Pin-chih Lin <johnylin@google.com>
2022-12-09 16:02:26 +00:00
Bard Liao 113064cbf7 topology2: cavs-sdw: add Speaker and Microphone pcm
Add Speaker PCM to cavs-sdw topology. We need to set NUM_SDW_AMPS=1 in
CMakeLists.txt if there is only one amplifier in the device and set
NUM_SDW_AMPS=2 if there are two amplifiers.
Set SDW_DMIC=1 if there is a SDW DMIC, like rt714 in the device.
The 2nd ALH copier stream name should be the same as the 1st ALH
copier, and no need to connect to the route.
The 2nd ALH copier data will be set to the 1st ALH copier's gateway config
in the aggregated mode.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
2022-12-09 15:54:18 +00:00
Bard Liao 1faf055755 topology2: cavs-sdw: use macro to define SDW jack stream and id
Define macro for SoundWire jack stream name and BE id.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
2022-12-09 15:54:18 +00:00
Bard Liao f0a010052b topology2: cavs-sdw: group route and pipeline index
A topology may be constructed by some .conf files. We may use a
duplicated route index or pipeline index by accident. This commit
suggests a rule to assign route and pipeline index.
We have a consistent pcm id. For example,
Jack out: 0
Jack in: 1
Speaker: 2
Microphone: 4

We can use a simple formula to assign the route and pipeline index
for each pcm.
The formula this commit suppests is pcm id * 10 ~ pcm id * 10 + 9.
That is 0 ~ 9 for pcm 0, 10 ~ 19 for pcm 1, and so on.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
2022-12-09 15:54:18 +00:00
Tomasz Leman 192fda25a8 west.yml: upgrade zephyr to 56284d7017
Zepych update: total of 40 commits.

Update needed before enabling power domains.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-09 15:50:22 +00:00
Marc Herbert 89ddee6961 .github/zephyr: git fetch more to fix version.h and reproducibility
We need the ability to reproduce CI builds easily.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-09 15:49:28 +00:00
Marc Herbert 09386bc0d9 Revert "xtensa-build-zephyr.py: west update --depth 5 --narrow"
This reverts commit ce28e09bd3.

This fixes Zephyr's git describe command and build reproducibility.

I tried fairly hard various git fetch options like --shallow-exclude
and --shallow-since but they did not save that much download (200MB at
best), required some hardcoding and most importantly they make complete
clones shallow again when invoked unconditionally. Not worth the
effort, build reproducibility is more important.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-12-09 15:49:28 +00:00
Rander Wang 8cdf8e1e17 dai: release llp slot when dai is free
At first llp slot is released by dai_dma_free for dai_free in
ipc4 path. Now dai_dma_free is removed from dai_free, so add
another function dai_release_llp_slot to free llp slot in
dai_free.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2022-12-09 12:49:58 +00:00
Rander Wang efe51fa90a ipc4: dai: use llp info to update llp slot in memory window
Don't query llp slot offset in each update function
and get it from llp info.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2022-12-09 12:49:58 +00:00
Rander Wang 2283996192 ipc4: dai: allocated unused llp slot to each stream
Current llp slot is allocated based on virtual index
in node id which is incorrect since different dai may
use the same virtual index. Now find the first unused
llp slot and assign it to stream and save the slot info
to avoid querying it for each update

Signed-off-by: Rander Wang <rander.wang@intel.com>
2022-12-09 12:49:58 +00:00