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platform:amd:enable acp SRAM 

Configure ACP sram access.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
This commit is contained in:
Kalva, DineshKumar 2022-12-08 15:26:26 +05:30 committed by Liam Girdwood
parent a992de9a05
commit 86203383a6
6 changed files with 29 additions and 22 deletions
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4
src/drivers/amd/rembrandt/acp_bt_dma.c
View File

@ -238,7 +238,7 @@ static int acp_dai_bt_dma_set_config(struct dma_chan_data *channel,
/* Transmit RINGBUFFER Address and size */
config->elem_array.elems[0].src =
(config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
bt_ringbuff_addr = (config->elem_array.elems[0].src | 0x01000000);
bt_ringbuff_addr = (config->elem_array.elems[0].src | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_BT_TX_RINGBUFADDR), bt_ringbuff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_BT_TX_RINGBUFSIZE), bt_buff_size);
@ -259,7 +259,7 @@ static int acp_dai_bt_dma_set_config(struct dma_chan_data *channel,
/* Receive RINGBUFFER Address and size */
config->elem_array.elems[0].dest =
(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
bt_ringbuff_addr = (config->elem_array.elems[0].dest | 0x01000000);
bt_ringbuff_addr = (config->elem_array.elems[0].dest | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_BT_RX_RINGBUFADDR), bt_ringbuff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_BT_RX_RINGBUFSIZE), bt_buff_size);

4
src/drivers/amd/rembrandt/acp_dma.c
View File

@ -463,14 +463,14 @@ static int dma_setup(struct dma_chan_data *channel,
if (dir == DMA_DIR_HMEM_TO_LMEM) {
/* Playback */
dma_config_dscr[dscr_strt_idx].dest_addr =
(dma_config_dscr[dscr_strt_idx].dest_addr & 0x0FFFFFFF);
(dma_config_dscr[dscr_strt_idx].dest_addr & ACP_DRAM_ADDRESS_MASK);
dma_cfg->base = dma_config_dscr[dscr_strt_idx].dest_addr | ACP_SRAM;
dma_cfg->wr_size = 0;
dma_cfg->rd_size = dma_cfg->size;
} else {
/* Capture */
dma_config_dscr[dscr_strt_idx].src_addr =
(dma_config_dscr[dscr_strt_idx].src_addr & 0x0FFFFFFF);
(dma_config_dscr[dscr_strt_idx].src_addr & ACP_DRAM_ADDRESS_MASK);
dma_cfg->base = dma_config_dscr[dscr_strt_idx].src_addr | ACP_SRAM;
dma_cfg->wr_size = dma_cfg->size;
dma_cfg->rd_size = 0;

4
src/drivers/amd/rembrandt/acp_sp_dma.c
View File

@ -226,7 +226,7 @@ static int acp_dai_sp_dma_set_config(struct dma_chan_data *channel,
/* Transmit RINGBUFFER Address and size*/
config->elem_array.elems[0].src = (config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
sp_buff_addr = (config->elem_array.elems[0].src | 0x01000000);
sp_buff_addr = (config->elem_array.elems[0].src | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_I2S_TX_RINGBUFADDR), sp_buff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_I2S_TX_RINGBUFSIZE), sp_buff_size);
@ -248,7 +248,7 @@ static int acp_dai_sp_dma_set_config(struct dma_chan_data *channel,
/* Receive RINGBUFFER Address and size*/
config->elem_array.elems[0].dest = (config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
sp_buff_addr = (config->elem_array.elems[0].dest | 0x01000000);
sp_buff_addr = (config->elem_array.elems[0].dest | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR), sp_buff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFSIZE), sp_buff_size);

2
src/platform/amd/rembrandt/include/platform/fw_scratch_mem.h
View File

@ -13,7 +13,7 @@
/* MAX number of DMA descriptors */
#define MAX_NUM_DMA_DESC_DSCR 64
#define SCRATCH_REG_OFFSET 0x1250000
#define ACP_SRAM 0x03800000
typedef struct acp_atu_grp_pte {
uint32_t low_part;
uint32_t high_part;

30
src/platform/amd/rembrandt/include/platform/lib/memory.h
View File

@ -18,13 +18,17 @@
/* physical DSP addresses */
#define IRAM_BASE 0x7F000000
#define IRAM_SIZE 0x20000
#define IRAM_SIZE 0x60000
#define DRAM0_BASE 0xE0000000
#define DRAM0_SIZE 0x7000
#define DRAM1_SIZE 0x29000
#define SRAM0_BASE 0x9FF00000
#define DRAM1_BASE 0xE0007000
#define DRAM1_SIZE 0x19000
#define SRAM1_BASE 0x60006000
#define SRAM1_SIZE 0x13A000
#define DMA0_BASE PU_REGISTER_BASE
#define DMA0_SIZE 0x4
@ -84,23 +88,23 @@
/* Heap section sizes for module pool */
#define HEAP_RT_COUNT8 0
#define HEAP_RT_COUNT16 4
#define HEAP_RT_COUNT32 4
#define HEAP_RT_COUNT64 5
#define HEAP_RT_COUNT16 48
#define HEAP_RT_COUNT32 48
#define HEAP_RT_COUNT64 32
#define HEAP_RT_COUNT128 60
#define HEAP_RT_COUNT256 32
#define HEAP_RT_COUNT512 8
#define HEAP_RT_COUNT1024 4
#define HEAP_RT_COUNT2048 2
#define HEAP_RT_COUNT512 4
#define HEAP_RT_COUNT1024 12
#define HEAP_RT_COUNT2048 12
/* Heap section sizes for system runtime heap */
#define HEAP_SYS_RT_COUNT64 4
#define HEAP_SYS_RT_COUNT512 26 /*rembrandt-arch*/
#define HEAP_SYS_RT_COUNT64 64
#define HEAP_SYS_RT_COUNT512 20 /*rembrandt-arch*/
#define HEAP_SYS_RT_COUNT1024 6
/* Heap configuration */
#define HEAP_SYSTEM_BASE SOF_STACK_BASE
#define HEAP_SYSTEM_SIZE 0x1000
#define HEAP_SYSTEM_BASE SRAM1_BASE
#define HEAP_SYSTEM_SIZE 0xE000
#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
#define HEAP_SYS_RUNTIME_SIZE (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
@ -115,7 +119,7 @@
HEAP_RT_COUNT2048 * 2048)
#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
#define HEAP_BUFFER_SIZE (0xB000)
#define HEAP_BUFFER_SIZE (0xF000)
#define HEAP_BUFFER_BLOCK_SIZE 0x180
#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)

7
src/platform/amd/rembrandt/rembrandt.x.in
View File

@ -100,8 +100,11 @@ MEMORY
org = SOF_STACK_END,
len = SOF_STACK_BASE - SOF_STACK_END,
sof_sdram1 :
org = HEAP_BUFFER_BASE + HEAP_BUFFER_SIZE,
len = DRAM1_SIZE- (HEAP_SYSTEM_SIZE +HEAP_SYS_RUNTIME_SIZE + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE + SOF_STACK_SIZE )
org = DRAM1_BASE,
len = DRAM1_SIZE
sof_sram1 :
org = SRAM1_BASE,
len = SRAM1_SIZE
static_uuid_entries_seg (!ari) :
org = UUID_ENTRY_ELF_BASE,
len = UUID_ENTRY_ELF_SIZE