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drivers: amd: enable acp SRAM 

Configure ACP sram access.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
This commit is contained in:
Kalva, DineshKumar 2022-12-08 14:32:29 +05:30 committed by Liam Girdwood
parent c91326bda2
commit a992de9a05
3 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/drivers/amd/rembrandt/acp_dma.c
View File

@ -109,7 +109,7 @@ static void dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
psrc_dscr[strt_idx].src_addr = src;
dest = (dest & ACP_DRAM_ADDRESS_MASK);
/* Known Data hack */
psrc_dscr[strt_idx].dest_addr = (dest | 0x01000000);
psrc_dscr[strt_idx].dest_addr = (dest | ACP_SRAM);
psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
/* Configure a single descrption */
dma_config_descriptor(strt_idx, 1, psrc_dscr, pdest_dscr);
@ -121,11 +121,11 @@ static void dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
tail = dma_cfg->sys_buff_size - dma_cfg->rd_size;
head = bytes - tail;
psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = tail;
psrc_dscr[strt_idx+1].src_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
psrc_dscr[strt_idx + 1].src_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
dest1 = dest+tail;
dest1 = (dest1 & ACP_DRAM_ADDRESS_MASK);
psrc_dscr[strt_idx+1].dest_addr = (dest1 | 0x01000000);
psrc_dscr[strt_idx+1].trns_cnt.bits.trns_cnt = head;
psrc_dscr[strt_idx + 1].dest_addr = (dest1 | ACP_SRAM);
psrc_dscr[strt_idx + 1].trns_cnt.bits.trns_cnt = head;
dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
dma_cfg->rd_size = 0;
@ -141,7 +141,7 @@ static void dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
src = dma_cfg->rd_ptr;
dest = dma_cfg->wr_ptr;
src = (src & ACP_DRAM_ADDRESS_MASK);
psrc_dscr[strt_idx].src_addr = (src | 0x01000000);
psrc_dscr[strt_idx].src_addr = (src | ACP_SRAM);
psrc_dscr[strt_idx].dest_addr = dest;
psrc_dscr[strt_idx].trns_cnt.bits.trns_cnt = bytes;
/* Configure a single descrption */
@ -159,7 +159,7 @@ static void dma_reconfig(struct dma_chan_data *channel, uint32_t bytes)
psrc_dscr[strt_idx+1].dest_addr = ACP_SYST_MEM_WINDOW + dma_cfg->phy_off;
psrc_dscr[strt_idx+1].trns_cnt.bits.trns_cnt = head;
src1 = (src1 & ACP_DRAM_ADDRESS_MASK);
psrc_dscr[strt_idx+1].src_addr = (src1 | 0x01000000);
psrc_dscr[strt_idx+1].src_addr = (src1 | ACP_SRAM);
dma_config_descriptor(strt_idx, 2, psrc_dscr, pdest_dscr);
dma_chan_reg_write(channel, ACP_DMA_DSCR_CNT_0, 2);
dma_cfg->wr_size = 0;
@ -424,7 +424,7 @@ static int dma_setup(struct dma_chan_data *channel,
sgelems->elems[dscr].src + ACP_SYST_MEM_WINDOW;
dest = sgelems->elems[dscr].dest;
dest = (dest & ACP_DRAM_ADDRESS_MASK);
dma_config_dscr[dscr_strt_idx + dscr].dest_addr = (dest | 0x01000000);
dma_config_dscr[dscr_strt_idx + dscr].dest_addr = (dest | ACP_SRAM);
dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32All = 0;
dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
sgelems->elems[dscr].size;
@ -438,7 +438,7 @@ static int dma_setup(struct dma_chan_data *channel,
src = sgelems->elems[dscr].src;
src = (src & ACP_DRAM_ADDRESS_MASK);
dma_config_dscr[dscr_strt_idx + dscr].src_addr =
(src | 0x01000000);/*rembrandt-arch*/
(src | ACP_SRAM);/*rembrandt-arch*/
dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.u32All = 0;
dma_config_dscr[dscr_strt_idx + dscr].trns_cnt.bits.trns_cnt =
sgelems->elems[dscr].size;
@ -464,14 +464,14 @@ static int dma_setup(struct dma_chan_data *channel,
/* Playback */
dma_config_dscr[dscr_strt_idx].dest_addr =
(dma_config_dscr[dscr_strt_idx].dest_addr & 0x0FFFFFFF);
dma_cfg->base = dma_config_dscr[dscr_strt_idx].dest_addr | 0x01000000;
dma_cfg->base = dma_config_dscr[dscr_strt_idx].dest_addr | ACP_SRAM;
dma_cfg->wr_size = 0;
dma_cfg->rd_size = dma_cfg->size;
} else {
/* Capture */
dma_config_dscr[dscr_strt_idx].src_addr =
(dma_config_dscr[dscr_strt_idx].src_addr & 0x0FFFFFFF);
dma_cfg->base = dma_config_dscr[dscr_strt_idx].src_addr | 0x01000000;
dma_cfg->base = dma_config_dscr[dscr_strt_idx].src_addr | ACP_SRAM;
dma_cfg->wr_size = dma_cfg->size;
dma_cfg->rd_size = 0;
}

2
src/drivers/amd/rembrandt/acp_dmic_dma.c
View File

@ -224,7 +224,7 @@ static int acp_dmic_dma_set_config(struct dma_chan_data *channel,
case DMA_DIR_MEM_TO_DEV:
config->elem_array.elems[0].dest =
(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
ring_buff_addr = (config->elem_array.elems[0].dest | 0x01000000);
ring_buff_addr = (config->elem_array.elems[0].dest | ACP_SRAM);
/* Load Ring buffer address */
io_reg_write(PU_REGISTER_BASE +
ACP_WOV_RX_RINGBUFADDR, ring_buff_addr);

4
src/drivers/amd/rembrandt/acp_hs_dma.c
View File

@ -224,7 +224,7 @@ static int acp_dai_hs_dma_set_config(struct dma_chan_data *channel,
/* Transmit RINGBUFFER Address and size*/
config->elem_array.elems[0].src = (config->elem_array.elems[0].src & ACP_DRAM_ADDRESS_MASK);
hs_buff_addr = (config->elem_array.elems[0].src | 0x01000000);
hs_buff_addr = (config->elem_array.elems[0].src | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_HS_TX_RINGBUFADDR), hs_buff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_HS_TX_RINGBUFSIZE), hs_buff_size_playback);
@ -248,7 +248,7 @@ static int acp_dai_hs_dma_set_config(struct dma_chan_data *channel,
/* Receive RINGBUFFER Address and size*/
config->elem_array.elems[0].dest =
(config->elem_array.elems[0].dest & ACP_DRAM_ADDRESS_MASK);
hs_buff_addr = (config->elem_array.elems[0].dest | 0x01000000);
hs_buff_addr = (config->elem_array.elems[0].dest | ACP_SRAM);
io_reg_write((PU_REGISTER_BASE + ACP_P1_HS_RX_RINGBUFADDR), hs_buff_addr);
io_reg_write((PU_REGISTER_BASE + ACP_P1_HS_RX_RINGBUFSIZE), hs_buff_size_capture);