Adds new start_position field based on which we assess whether
we should throw an xrun. It fixes rare cases of xruns on release
with timer scheduled pipelines.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Checks if DMA channel exists in dai_prepare. This way we will
avoid exception in case DAI config hasn't been called before.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes ICL topology to use 3 periods for buffer connected to ALH DAI.
This topology has been forgotten, when such changes were done.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Fixes SSP format and used pipeline macro in CML topologies.
Fixes: cfe81f5127 ("topology: cml: cnl: use 3 periods for SSP, DMIC and ALH DAIs")
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
New platforms like TigerLake will need 3k RSA key for signing.
Generate new keys for SOF public key.
Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
For DW-DMA without hardware linked list support we need
to manually reload linked list items after every interrupt.
It's very time-sensitive and even the slightest drift can
cause glitches, so this patch moves lli reload routine
to be called from DMA domain as an interrupt callback.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds irq_callback to dma_chan_data. It's called by the
DMA domain right after receiving an interrupt, so should
execute very time-sensitive operations.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
The SAI is a hardware DAI on the i.MX platform. This commit brings
the initial support for the SAI.
Current limitations:
-> Hardware FIFO watermark is hardcoded to HALF FIFO size
-> current codec only support stereo channels
-> slot size hardcoded to 32 bit
-> clock divider is set to 8
Signed-off-by: Guido Roncarolo <guido.roncarolo@nxp.com>
Signed-off-by: Jerome Laclavere <jerome.laclavere@nxp.com>
Initially I have hardcoded the specific values required for the ESAI.
That however is highly inflexible.
This commit refactors that to allow a more flexible declaration so that
other DMA clients can also get their proper interrupt numbers.
Only hardware which delivers its DMA interrupts via IRQ_STEER is
supported, however on this platform that is fine (all DMA channels
deliver their interrupts as shared interrupts via IRQ_STEER).
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
On the pipelines which use EDMA, the EDMA interrupts are the ones which
schedule all the copies and processing happening inside a pipeline.
This commit enables the EDMA controller to schedule copies on this
platform.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Fixes tasks initialization for connected pipelines.
If we play on pipeline, which is not the owner of
the scheduling component, then the pipeline_prepare()
is not called on pipe owning that component and tasks
stay unitialized.
Fixes: de7d4c95cf ("pipeline: allocate pipe_task only if needed")
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Add alignment option for memory requests.
Fix alloc definitions for UT.
Function definitions were using defines in their body
which blocked usage of const values in said defines.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Fix alloc definitions for host build.
Function definitions were using defines in their body
which blocked usage of const values in said defines.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This is to optimize memory consumption from this driver. With 32
channels we would have needed a memory block >1024 bytes in size to
allocate the dma_chan_data array. However 16 channels (which means
allocating a smaller block) should be enough for everyone.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
The dummy DMA is a software-based DMA which acts as a host DMA. This
one can be implemented in software alone because all host physical
address space (at least the RAM portion) is accessible directly from
the DSP on this platform.
The driver works by taking the physical addresses for both the source
and destination addresses from the elems. This works because no paging
is enabled on the DSP side, and because the page tables interpretation
allows these elements to actually have physical addresses on the host
side. Given these addresses, the copy itself is done synchronously on
the DSP within a memcpy_s call.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Enabling this config option changes the way the SG elems are generated,
such that the host addresses in the elems are actual, physical
addresses.
This is required by the Dummy DMA driver, which can only operate with
said physical addresses.
This commit enables the config option and fixes compile errors which
appeared after this enabling.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
With new schedulers implementations we don't need to trigger
pipeline in atomic context anymore.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Switches from DMA multi channel domain to single channel
as the scheduling source for one of the low latency schedulers
for cAVS platforms.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of DMIC DAI periods from 2 to 3. This way
we can support both timer and new single DMA channel
scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP and DMIC DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP, DMIC and ALH DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP, DMIC and ALH DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP and DMIC DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Uses DAI_PERIODS in calculation of DAI buffer size.
In case the DAI_PERIODS value is undefined, we use
DAI_DEFAULT_PERIOD value of 2.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Fixes pipe-dai-capture and pipe-dai-playback pipelines
to use passed DAI_PERIODS value instead of hardcoded.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds implementation of DMA single channel scheduling domain.
This domain allows to schedule all the tasks on all the cores
on single DMA channel interrupt. This way we have only one
interrupt source and we don't need to worry about handling
many interrupts. We always select the channel with the lowest
period. This domain cannot be used with the DMAs, which require
to manually reload the next data to be transferred e.g. DW-DMA
on BYT or HSW.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Some ll scheduling domains require to have interrupt cleared
right at the beginning of handler. Clear domain earlier to
fulfill that requirement.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds DMA channel period value to dma_chan_data.
We can now easily retrieve the period value of
DMA channel transfers.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds new NOTIFIER_ID_DMA_DOMAIN_CHANGE. This id will be used
by DMA single channel scheduling domain.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Fixes return value of platform_timer_set and arch_timer_set functions.
Change was introduced for cAVS platforms, which accidentally broke
these functions for other platforms. The intention of this functions
is to return value of set ticks, so the timer scheduler can check
for delays.
Fixes: 75188e2243 ("timer: rework timer_set() so it verifies requested ticks")
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
For the moment, the EDMA will only be used with one client -- the ESAI.
The IRQ number for both of the channels corresponding to the ESAI (as
well as the controller name) will be the same, and will map to interrupt
442 (which, according to the calculations required by IRQ_STEER, map to
interrupt 442 % 64 = 58 on controller 442 / 64 = 6).
In the future we should make this more flexible.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
This is a hardware DMA controller on the i.MX platform. This one is
capable of doing mem-to-dev and dev-to-mem copies of any data.
This commit contains most of the initial implementation but a few things
related to IRQ handling (such as IRQ numbers).
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
DMA controllers on the i.MX8 platform provide separate interrupts per
channel which may fall on different IRQ_STEER interrupt lines. Due to
the current architecture of the IRQ_STEER driver, this means the
channels may have their interrupts fall on different interrupt
controllers.
This commit allows setting an interrupt controller name per interrupt.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
These functions are 16-bit counterparts to the preexisting 32-bit
functions io_reg_update_bits and dma_chan_reg_update_bits and are
intended to be used for general (in the former case) and DMA (in the
latter) 16-bit registers.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Tomasz Lauda