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topology: intel-generic-dmic: use 3 periods for DMIC DAIs 

Changes number of DMIC DAI periods from 2 to 3. This way
we can support both timer and new single DMA channel
scheduling.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda 2019-09-20 11:19:34 +02:00 committed by Janusz Jankowski
parent 5a3546595b
commit b23a6cc277
1 changed files with 13 additions and 12 deletions
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25
tools/topology/platform/intel/intel-generic-dmic.m4
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@ -12,25 +12,26 @@ define(DMIC_DAI_LINK_16k_ID, `7')
# Define the pipelines
#
dnl PIPELINE_PCM_ADD(pipeline,
dnl PIPELINE_PCM_DAI_ADD(pipeline,
dnl pipe id, pcm, max channels, format,
dnl period, priority, core,
dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
dnl time_domain, sched_comp)
dnl dai type, dai_index, dai format,
dnl dai periods, pcm_min_rate, pcm_max_rate,
dnl pipeline_rate, time_domain)
# Passthrough capture pipeline using max channels defined by CHANNELS.
# Set 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4,
PIPELINE_PCM_DAI_ADD(sof/pipe-eq-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC_DAI_LINK_48k_ID, CHANNELS, s32le,
1000, 0, 0, 48000, 48000, 48000)
1000, 0, 0, DMIC, 0, s32le, 3, 48000, 48000, 48000)
# Passthrough capture pipeline using max channels defined by CHANNELS.
# Schedule with 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4,
PIPELINE_PCM_DAI_ADD(sof/pipe-eq-capture-16khz.m4,
DMIC_PIPELINE_16k_ID, DMIC_DAI_LINK_16k_ID, CHANNELS, s32le,
1000, 0, 0, 16000, 16000, 16000)
1000, 0, 0, DMIC, 1, s32le, 3, 16000, 16000, 16000)
#
# DAIs configuration
@ -39,20 +40,20 @@ PIPELINE_PCM_ADD(sof/pipe-eq-capture-16khz.m4,
dnl DAI_ADD(pipeline,
dnl pipe id, dai type, dai_index, dai_be,
dnl buffer, periods, format,
dnl deadline, priority, core)
dnl deadline, priority, core, time_domain)
# capture DAI is DMIC 0 using 2 periods
# capture DAI is DMIC 0 using 3 periods
# Buffers use s32le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_48k_ID, DMIC, 0, dmic01,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 2, s32le,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_48k_ID), 3, s32le,
1000, 0, 0, 48000, 48000, 48000)
# capture DAI is DMIC 1 using 2 periods
# capture DAI is DMIC 1 using 3 periods
# Buffers use s32le format, with 16 frame per 1000us on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
DMIC_PIPELINE_16k_ID, DMIC, 1, dmic16k,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_16k_ID), 2, s32le,
concat(`PIPELINE_SINK_', DMIC_PIPELINE_16k_ID), 3, s32le,
1000, 0, 0, 16000, 16000, 16000)
dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)