63c9353240
On UP Xtreme board current code only supports PCH UART debug port. But this board has two extra UART ports behind SIO chip F81801. This patch added required initialization for the SIO chip to enable UART on SIO. It can be enabled through platform data during stitching. For exmaple, "-p 0xAA000210" parameter in stitching will select PCH UART2. "-p 0xAA00FF10" parameter will select SIO COM1 as debug device. "-p 0xAA00FE10" parameter will select SIO COM2 as debug device. Signed-off-by: Maurice Ma <maurice.ma@intel.com> |
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.. | ||
AcpiTables | ||
CfgData | ||
Include | ||
Library | ||
Script | ||
BoardConfig.py | ||
CoffeelakeBoardPkg.dec | ||
Readme.md |
Readme.md
Whiskeylake(WHL)/CoffeeLake(CFL)
Clone source
Building
- python BuildLoader.py build cfl
- NOTE: Build target(cfl) is common for both WHL/CFL
- NOTE: For UEFI payload, please refer to UefiPayloadPkg in edk2 repo. In UefiPayloadPkg/BuildAndIntegrationInstructions.txt, refer to section.
Stitching
- Prepare/Download UEFI based IFWI for WHL or CFL
- python Platform/CoffeelakeBoardPkg/Script/StitchLoader.py
-i
EXISTING IFWI IMAGE
-oSBL IFWI IMAGE
-s Outputs/cfl/SlimBootloader.bin - NOTE: Please make sure that this stitching method will work only if Boot Guard in the base image is not enabled, and the silicon is not fused with Boot Guard enabled.
Flashing
- Flash generated
SBL IFWI IMAGE
to the target board using DediProg SF100 or SF600 programmer.