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Maurice Ma 63c9353240 [CFL] Enable UPX SIO debug UART for COM1 and COM2 
On UP Xtreme board current code only supports PCH UART debug port.
But this board has two extra UART ports behind SIO chip F81801.
This patch added required initialization for the SIO chip to enable
UART on SIO. It can be enabled through platform data during stitching.
For exmaple,
  "-p 0xAA000210" parameter in stitching will select PCH UART2.
  "-p 0xAA00FF10" parameter will select SIO COM1 as debug device.
  "-p 0xAA00FE10" parameter will select SIO COM2 as debug device.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
 		2019-10-01 13:26:23 -07:00
..
ApollolakeBoardPkg [APL] Fix boot option settings for ACRN 2019-09-11 06:04:57 -07:00
CoffeelakeBoardPkg [CFL] Enable UPX SIO debug UART for COM1 and COM2 2019-10-01 13:26:23 -07:00
CommonBoardPkg Add DBG2 ACPI table infrastructure 2019-09-16 19:40:59 -07:00
QemuBoardPkg Update GenContainer.py to create container BOOT image 2019-10-01 10:33:17 -07:00