This supports XCODE toolchain in Mac OS.
- Tested on macOS Catalina version 10.15.2
- Tested with Apple clang version 11
- Verified QEMU target
Signed-off-by: Aiden Park <aiden.park@intel.com>
Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform
Signed-off-by: Guo Dong <guo.dong@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added required code flow to prepare to enable DMA
protection for CFL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For CFL, VT-d PMR cannot be fully enabled
before FspSiliconInit. So it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added required code flow to prepare to enable DMA
protection for APL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For APL, since VT-d is only enabled
in FspSiliconInit, it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
As part of the DMA memory protection, it needs API to enable/disable
DMA protection. This patch simplified the API to do that using
SetDmaProtection().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added the VTd PMR memory protection library. It can be
used to support DMA memory protection feature later on. It also
enabled basic build on APL platform so that it can be tested as part
of the automatic build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
platform security discovery driver having bug it was wrongly doing
pointer arithmetic and causing memory overwrite. this may cause
intermittent fault.
Removing ZeroMem call since its not required, ACPI table is already
ZeroMem allocated from PSD aslc code.
Signed-off-by: Prakash Chandra <prakash1.chandra@intel.com>
Since SgxLib has a dependency on platform
specific FSP header files it should not be
used as a common platform library. This
patch preserves the same functionality as
before but just moves the library to be
silicon specific.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
When USB devices are used to wake from S3 and S4, PME_B0_STS
GPE bit is set and is causing SMI storm which is resulting intel
board hang during wake from S3 and S4.
Clearing PME_B0_EN during wake helped fix the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code does not clear firmware update trigger incase
of failures like, capsule image not found or capsule image
authentication failed.
Code is modified to fix this issue. As part of this change,
EndFirmwareUpdate function is moved from platform code to
core firmwareupdate.c. EndFirmwareUpdate function will call
ClearFwUpdateTrigger and this will end firmware update.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added code to:
- Trigger FWU using sticky register in SBL Shell
- Detect FWU mode using combination of sticky register and state
machine
- Clear the trigger flag at the end of FWU
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
After erasing flash on QEMU, it needs to be returned to normal
read state to allow normal read access. However, this is missing
in current SBL QEMU SpiFlashLib. This patched added the code to
switch back to read mode. It also fixed#552.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will allow update PSS table in a common way.
For a platform specific power calculation,
a function pointer can be provided.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently each component inside capsule is identified with GUID
but going forward support is being added to update multiple components
inside sbl and container, so larger number of GUID's are required, also
GUID need to be passed for unknown components through command line.
Instead 4 character unique signature from flash map that is passed
through command line to indentify the component is added to the
component header. This signature is used during runtime to indentify
the component from flash map and container.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch enabled Visual Studio 2017 Community 2017 build support.
The following were done:
- Added new method to detect VS2017 installation path and version
- Droped VS2005, VS2008, VS2010 and VS2012 build support. Only
VS2013 and VS2015 are supported.
- Fixed build issue in FspApiLib due to new compiler optimizations
- Synced the build support for QEMU FSP patch
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add a common SmbusLib support for Intel PCH
Define PLT_MEDIUM_MISC_TYPE in device table for
devices that are not for OS boot.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch does the following
1) Enable triggering firmware update from OS
2) When firmware update mode is given control, state machine
is set to capsule processing and firmware update platform
specific trigger is cleared. State machine will be used
hereafter to track firmware update
3) Created CheckStateMachine method in BoardSupportLib.c to
check state machine to see if firmware update is in progress
and set boot mode to firmware update.
4) Removed CMOS way of triggering firmware update and wrote code
to use Over-Clocking WDT Scratchpad (OC_WDT_SCRATCH) bits for
triggering firmware update
5) Update shell fwupdate command to use OC_WDT_SCRATCH bits.
6) Removed extra reset during sbl firmware update
7) Removed reset after updating configuration data update
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This issue happens under two conditions
1. Unicode language environment in Windows
2. A python calls 'BaseTools/toolsetup.bat'
(In EDKII, edksetup.bat directly in Windows command shell)
- 'BuildLoader.py' calls 'BaseTools/toolsetup.bat' in a subprocess
- 'BaseTools/toolsetup.bat' calls 'nmake cleanall'
- 'cleanall' target runs 'python NmakeSubdirs.py' directly
- 'NmakeSubdirs.py' creates multi-threads
- The threads create another subprocesses
But, one of multi-threads is on deadlock when python handles stdout and
stderr in a subprocess pipe only if the output includes unicode chars.
Therefore, only stderr will be handled in the pipe same as a single
thread call.
Signed-off-by: Aiden Park <aiden.park@intel.com>
HASH_STORE_TABLE is updated and HASH_STORE_DATA is added
to provide info with variable length sizes. Usage bits would
notify for multiple component/key using the same hash.
These data structure would optimize the hash store size
in storage.
PcdHashStoreSize would define the size of Hash store
to allocate in bios bootup.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
This is a follow-up to the previous WOL commit. The previous
implementation is more LeafHill specific. This patch further
added configuration data to control how wake up signal is mapped
into each PCIE root port. And the ASL code has been adjusted to
utilize that info so that the code can be more generic for all
other platforms.
The current default configuration for PCIE wake signal is aligned
with LeafHill CRB board. For other borads, to enable it properly,
it is required to override the wake signal configuration using DLT.
Test has been done on LeafHill to do WOL with yocto image. It worked
as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SerialPortLib sets UART Scratch Register to a known value at the first
initialization to avoid unnecessary re-initialization afterward. But,
one of Windows driver(SIO) re-configures UART Registers while the Scratch
Register is preserved. As a result, SBL skips serial port initialization
after restarting from Windows.
Therefore, force to initialize Serial Port at Stage1A all the time simply.
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is an issue with Vbt.bin in MR5; MR6 has this fixed.
Test: compiles OK, boots Linux OK.
Signed-off-by: Ursula Maplehurst <ursula@kangatronix.co.uk>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
power button 4 second press will cause power button override
bit to set in PM1 status register, this bit is not cleared on
reset and is causing SMI storm during booting to OS.
Power button override bit if set is cleared now in stage1b and
this fixed the SMI storm issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch switched to use SerialPortLib in BootloaderCommonPkg for
QEMU and CFL platforms. For APL platform, it can also use this common
library. However, it has an optimized SerialPortLib with FIFO enabled.
So for APL, it still uses its SOC specific library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch used the common API GetTimeStampFrequency() to get CPU
TSC frequency instead of the original GetCpuTscFreqency(). As part
of it, all SOC specific instances for GetCpuTscFreqency() were
removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The WHL(and CFL-R) has its own SpiFlashLib, but it's almost identical
to common SpiFlashLib except of silicon specific part.
Therefore, CoffeelakePkg will have its own PchSpiLib and re-use common
SpiFlashLib.
- Remove CoffeelakePkg SpiFlashLib and related files
- Use commmon SpiFlashLib
- Use CoffeelakePkg SpiFlashLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
QEMU has its own SpiFlashLib and SpiFlashLib.h file.
But, the header file is identical to the one in Silicon/CommonSocPkg.
Therefore, remove QEMU's one and re-use the common header file from
Silicon/CommonSocPkg.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
Platform Device structure PLT_DEVICE supports both PCI and MMIO formats.
But, SpiConstructor gets SPI device info from Platform Device Table
and it always assumes the info as a PCI format. This patch is to support
both formats.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Remove Silicon specific part from SpiFlashLib and use separate
PchSpiLib for Silicon specific part
- Remove Silicon specific code from SpiFlashLib
- Use PchSpiLib for Silicon specific part
- Remove unnecessary ScSpiCommon.h file
Signed-off-by: Aiden Park <aiden.park@intel.com>
Most of PCH SPI controller are using same mechanism to access SPI BAR
and to control BiosWriteProtect by using SPI PCI device/function.
But, a certain Silicon may use different way to access them.
ex) SPI BAR from LPC A reg, BiosWriteProtect from LPC B reg
Split SpiFlashLib into two parts.
- SpiFlashLib for common part
- PchSpiLib for silicon dependent part
This patch is to prepare the split.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This is prerequisite step to clean-up SpiFlashLib.
- Copy from BootloaderCommonPkg to Silicon/CommonSocPkg.
No code change at all.
- Keep the existing BootloaderCommonPkg SpiFlashLib.
To avoid build failure on existing boards.
The existing boards will use new one at the final clean-up stage.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On UP Xtreme board current code only supports PCH UART debug port.
But this board has two extra UART ports behind SIO chip F81801.
This patch added required initialization for the SIO chip to enable
UART on SIO. It can be enabled through platform data during stitching.
For exmaple,
"-p 0xAA000210" parameter in stitching will select PCH UART2.
"-p 0xAA00FF10" parameter will select SIO COM1 as debug device.
"-p 0xAA00FE10" parameter will select SIO COM2 as debug device.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Removing hard code in PrepareBuildComponentBin.py, so it could
support other platforms. And enhance its logic to support to
run in different places.
Moving repo and commit information to driver INF so this script
could reuse code to support different drivers.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch enabled very basic support to boot UP Xtreme (URL:
https://up-board.org/up-xtreme). Lots of porting are still required.
At this point, it can boot to OsLoader shell on PCH debug UART2 on
UP Xtreme board. It can also boot Ubuntu 18.04 and Yocto image.
Since there is no board ID check for UPX board, fixed Platform ID needs
to be specified during stitching. Here 0x10 is used for UPX Platform ID.
EX:
python Platform\CoffeelakeBoardPkg\Script\StitchLoader.py -i
XtremeBios.bin -s Outputs\cfl\SlimBootloader.bin -p 0xaa000210 -o ifwi.bin
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
S4 resume sets PWRBTN_EN. And since SCI_EN is set to 0,
this situation will generate spurious SMI# once GblSmi
is enabled.
Also moving RestoreS3regs before ProcessAllLocks, as SMI_LOCK
setting will prevent enabling GblSmi on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Generate NHLT(Non HD audio Link Table) depending on CFGDATA
- Add HDA_CFG_DATA for HDA and NHLT
- Create NHLT depending on config data value
HdaLib is from edk2-platforms devel-IntelAtomProcessorE3900 branch.
- Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
- Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/
Include/Private/Library/DxeScHdaNhlt.h
Include/Private/Library/ScHdaLib.h
Include/Private/ScHdaEndpoints.h
Private/DxeScHdaLib/ScHdaEndpoints.c
Private/DxeScHdaLib/ScHdaLib.c
ScInit/Dxe/ScHda.c
Signed-off-by: Aiden Park <aiden.park@intel.com>
* [CFL] Fix typecasting bug in IsSgxFeatureCtrlSet()
Fix BOOLEAN typecasting bug in IsSgxFeatureCtrlSet() and add DEBUG_WARNs
when certain checks fail.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Add microcode patch for CFL-S A stepping
Microcode patch for CFL-S A stepping was missing.
This was causing an issue with enabling Intel(R) SGX even when it was
enabled in the config. Hence, added the patch.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
Aiden Park