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Update SMM HOB support (#616) 

Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform

Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is contained in:
Guo Dong 2020-03-31 11:21:06 -07:00 committed by GitHub
parent dc190f6233
commit f6b08d1792
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 104 additions and 30 deletions
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48
BootloaderCommonPkg/Include/Guid/SmmInformationGuid.h
View File

@ -21,9 +21,10 @@ extern EFI_GUID gSmmInformationGuid;
#define SMM_FLAGS_4KB_COMMUNICATION BIT0
typedef enum {
MEM,
IO,
PCICFG
REG_TYPE_MEM,
REG_TYPE_IO,
REG_TYPE_PCICFG,
REG_TYPE_MMIO,
} REG_TYPE;
typedef enum {
@ -35,22 +36,48 @@ typedef enum {
#pragma pack(1)
///
/// Generic Address Space
/// SMI control register
///
typedef struct {
UINT8 RegType;
UINT8 RegWidth;
/// The bit value for Global SMI Enable (GBL_SMI_EN)
UINT8 SmiGblPos;
/// The bit value for APMC Enable (APMC_EN).
/// The bit index for APMC Enable (APMC_EN).
UINT8 SmiApmPos;
/// The bit value for End of SMI (EOS)
/// The bit index for Global SMI Enable (GBL_SMI_EN)
UINT8 SmiGblPos;
/// The bit index for End of SMI (EOS)
UINT8 SmiEosPos;
UINT8 Rsvd[3];
/// IO based address for SMM control and enable register
/// Address for SMM control and enable register
UINT32 Address;
} SMI_CTRL_REG;
///
/// SMI status register
///
typedef struct {
UINT8 RegType;
UINT8 RegWidth;
/// The bit index for APM Status (APM_STS).
UINT8 SmiApmPos;
UINT8 Rsvd[5];
/// Address for SMM status register
UINT32 Address;
} SMI_STS_REG;
///
/// SMI lock register
///
typedef struct {
UINT8 RegType;
UINT8 RegWidth;
/// The bit index for SMI Lock (SMI_LOCK)
UINT8 SmiLockPos;
UINT8 Rsvd;
/// Register address for SMM SMI lock
UINT32 Address;
} SMI_LOCK_REG;
typedef struct {
UINT8 Revision;
UINT8 Flags;
@ -58,8 +85,11 @@ typedef struct {
UINT32 SmmBase;
UINT32 SmmSize;
SMI_CTRL_REG SmiCtrlReg;
SMI_STS_REG SmiStsReg;
SMI_LOCK_REG SmiLockReg;
} LDR_SMM_INFO;
#pragma pack()
#endif

1
BootloaderCorePkg/Stage2/Stage2Support.c
View File

@ -549,6 +549,7 @@ BuildExtraInfoHob (
// Build SMMRAM info Hob
SmmInfoHob = BuildGuidHob (&gSmmInformationGuid, sizeof (LDR_SMM_INFO));
if (SmmInfoHob != NULL) {
ZeroMem (SmmInfoHob, sizeof (LDR_SMM_INFO));
PlatformUpdateHobInfo (&gSmmInformationGuid, SmmInfoHob);
}

47
Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -1588,29 +1588,48 @@ UpdateLoaderPlatformInfo (
/**
Update loader SMM info.
@param[out] SmmInfoHob pointer to SMM information HOB
@param[out] LdrSmmInfo pointer to SMM information HOB
**/
VOID
UpdateSmmInfo (
OUT LDR_SMM_INFO *SmmInfoHob
OUT LDR_SMM_INFO *LdrSmmInfo
)
{
if (LdrSmmInfo == NULL) {
return;
}
LdrSmmInfo->SmmBase = MmioRead32 (TO_MM_PCI_ADDRESS (0x00000000) + TSEG) & ~0xF;
LdrSmmInfo->SmmSize = MmioRead32 (TO_MM_PCI_ADDRESS (0x00000000) + BGSM) & ~0xF;
LdrSmmInfo->SmmSize -= LdrSmmInfo->SmmBase;
LdrSmmInfo->Flags = SMM_FLAGS_4KB_COMMUNICATION;
DEBUG ((DEBUG_ERROR, "Stage2: SmmRamBase = 0x%x, SmmRamSize = 0x%x\n", LdrSmmInfo->SmmBase, LdrSmmInfo->SmmSize));
SmmInfoHob->SmmBase = MmioRead32 (TO_MM_PCI_ADDRESS (0x00000000) + TSEG) & ~0xF;
SmmInfoHob->SmmSize = MmioRead32 (TO_MM_PCI_ADDRESS (0x00000000) + BGSM) & ~0xF;
SmmInfoHob->SmmSize -= SmmInfoHob->SmmBase;
SmmInfoHob->Flags = SMM_FLAGS_4KB_COMMUNICATION;
DEBUG ((DEBUG_INFO, "SmmRamBase = 0x%x, SmmRamSize = 0x%x\n", SmmInfoHob->SmmBase, SmmInfoHob->SmmSize));
//
// Update the HOB with smi ctrl register data
// Update smi ctrl register data
//
SmmInfoHob->SmiCtrlReg.RegType = IO;
SmmInfoHob->SmiCtrlReg.RegWidth = WIDE32;
SmmInfoHob->SmiCtrlReg.SmiGblPos = B_SMI_EN_GBL_SMI;
SmmInfoHob->SmiCtrlReg.SmiApmPos = B_SMI_EN_APMC;
SmmInfoHob->SmiCtrlReg.SmiEosPos = B_SMI_EN_EOS;
SmmInfoHob->SmiCtrlReg.Address = (UINT32)(ACPI_BASE_ADDRESS + R_SMI_EN);
LdrSmmInfo->SmiCtrlReg.RegType = (UINT8)REG_TYPE_IO;
LdrSmmInfo->SmiCtrlReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiCtrlReg.SmiGblPos = (UINT8)HighBitSet32 (B_SMI_EN_GBL_SMI);
LdrSmmInfo->SmiCtrlReg.SmiApmPos = (UINT8)HighBitSet32 (B_SMI_EN_APMC);
LdrSmmInfo->SmiCtrlReg.SmiEosPos = (UINT8)HighBitSet32 (B_SMI_EN_EOS);
LdrSmmInfo->SmiCtrlReg.Address = (UINT32)(ACPI_BASE_ADDRESS + R_SMI_EN);
//
// Update smi status register data
//
LdrSmmInfo->SmiStsReg.RegType = (UINT8)REG_TYPE_IO;
LdrSmmInfo->SmiStsReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiStsReg.SmiApmPos = (UINT8)HighBitSet32 (B_SMI_STS_APMC);
LdrSmmInfo->SmiStsReg.Address = (UINT32)(ACPI_BASE_ADDRESS + R_SMI_STS);
//
// Update smi lock register data
//
LdrSmmInfo->SmiLockReg.RegType = (UINT8)REG_TYPE_MMIO;
LdrSmmInfo->SmiLockReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiLockReg.SmiLockPos = (UINT8)HighBitSet32 (B_PMC_GEN_PMCON_2_SMI_LOCK);
LdrSmmInfo->SmiLockReg.Address = (UINT32)(PMC_BASE_ADDRESS + R_PMC_GEN_PMCON_2);
}

31
Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -246,7 +246,7 @@ STATIC SMMBASE_INFO mSmmBaseInfo = {
STATIC S3_SAVE_REG mS3SaveReg = {
{ BL_PLD_COMM_SIG, S3_SAVE_REG_COMM_ID, 1, 0 },
{ { IO, WIDE32, { 0, 0}, (ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN), 0x00000000 } }
{ { REG_TYPE_IO, WIDE32, { 0, 0}, (ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN), 0x00000000 } }
};
UINT8
@ -1858,15 +1858,32 @@ UpdateSmmInfo (
LdrSmmInfo->SmmSize -= LdrSmmInfo->SmmBase;
LdrSmmInfo->Flags = SMM_FLAGS_4KB_COMMUNICATION;
DEBUG ((DEBUG_ERROR, "Stage2: SmmRamBase = 0x%x, SmmRamSize = 0x%x\n", LdrSmmInfo->SmmBase, LdrSmmInfo->SmmSize));
//
// Update the HOB with smi ctrl register data
// Update smi ctrl register data
//
LdrSmmInfo->SmiCtrlReg.RegType = IO;
LdrSmmInfo->SmiCtrlReg.RegWidth = WIDE32;
LdrSmmInfo->SmiCtrlReg.SmiGblPos = B_ACPI_IO_SMI_EN_GBL_SMI;
LdrSmmInfo->SmiCtrlReg.SmiApmPos = B_ACPI_IO_SMI_EN_APMC;
LdrSmmInfo->SmiCtrlReg.SmiEosPos = B_ACPI_IO_SMI_EN_EOS;
LdrSmmInfo->SmiCtrlReg.RegType = (UINT8)REG_TYPE_IO;
LdrSmmInfo->SmiCtrlReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiCtrlReg.SmiGblPos = (UINT8)HighBitSet32 (B_ACPI_IO_SMI_EN_GBL_SMI);
LdrSmmInfo->SmiCtrlReg.SmiApmPos = (UINT8)HighBitSet32 (B_ACPI_IO_SMI_EN_APMC);
LdrSmmInfo->SmiCtrlReg.SmiEosPos = (UINT8)HighBitSet32 (B_ACPI_IO_SMI_EN_EOS);
LdrSmmInfo->SmiCtrlReg.Address = (UINT32)(ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_EN);
//
// Update smi status register data
//
LdrSmmInfo->SmiStsReg.RegType = (UINT8)REG_TYPE_IO;
LdrSmmInfo->SmiStsReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiStsReg.SmiApmPos = (UINT8)HighBitSet32 (B_ACPI_IO_SMI_STS_APM);
LdrSmmInfo->SmiStsReg.Address = (UINT32)(ACPI_BASE_ADDRESS + R_ACPI_IO_SMI_STS);
//
// Update smi lock register data
//
LdrSmmInfo->SmiLockReg.RegType = (UINT8)REG_TYPE_MMIO;
LdrSmmInfo->SmiLockReg.RegWidth = (UINT8)WIDE32;
LdrSmmInfo->SmiLockReg.SmiLockPos = (UINT8)HighBitSet32 (B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK);
LdrSmmInfo->SmiLockReg.Address = (UINT32)(PCH_PWRM_BASE_ADDRESS + R_PMC_PWRM_GEN_PMCON_B);
}
/**

5
Silicon/ApollolakePkg/Include/ScRegs/RegsPmc.h
View File

@ -42,6 +42,8 @@
#define R_PMC_BASE 0x10 ///< BAR0
#define R_PMC_ACPI_BASE 0x20 ///< BAR2
#define R_PMC_GEN_PMCON_1 0x1020 ///< General PM Configuration 1
#define R_PMC_GEN_PMCON_2 0x1024 ///< General PM Configuration 2
#define B_PMC_GEN_PMCON_2_SMI_LOCK BIT4 ///< SMI LOCK
#define R_PMC_BIOS_SCRATCHPAD 0x1090 ///< BIOS_SCRATCHPAD
#define B_PMC_GEN_PMCON_RTC_PWR_STS BIT2 ///< RTC Power Status
@ -70,6 +72,9 @@
#define B_SMI_EN_APMC BIT5 ///< APMC Enable
#define B_SMI_EN_SWSMI_TMR BIT6 ///< Software SMI Timer Enable
#define R_SMI_STS 0x44 ///< SMI Status
#define B_SMI_STS_APMC BIT5 ///< APMC status
#define R_TCO_STS 0x64 ///< TCO Timer Status
#define B_TCO_STS_SECOND_TO BIT17 ///< Second Timeout Status
#define R_TCO1_CNT 0x68 ///< TCO Control

2
Silicon/CoffeelakePkg/Include/Register/PchRegsPmc.h
View File

@ -45,6 +45,8 @@
#define B_ACPI_IO_SMI_EN_EOS BIT1
#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
#define R_ACPI_IO_SMI_STS 0x34
#define R_ACPI_IO_GPE_CNTL 0x40
#define R_ACPI_IO_OC_WDT_CTL 0x54