This patch fixed link error for APL NOOPT build due to compiler
intrinsics functions. However, due to APL hardware requirements,
it is not feasible to fit NOOPT build into real flash. This
patch will not fix the NOOPT build error caused by code size issue.
For example, the following error might still occur for APL NOOPT
build:
Invalid the required fv image size 0xe3b0 exceeds the set fv image
size 0x6000
The APL SOC requires Stage1A to fit into 32KB. Since FSP-T will take
8KB, it only gives 24KB for SBL Stage1A code. NOOPT build will create
about 56KB for Stage1A, and it is impossible to fit into the layout.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch expanded HECI service to include send, receive and
reset interface functions. This helps in making firmwareupdatelib.c
and PSDlib common across platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The structure of ME_BIOS_PAYLOAD varies on silicons. So, it's moved to
silicon directory and common structures are in MeBiosPayloadDataCommon.h.
- MeBiosPayloadDataCommon.h in CommonSocPkg
- MeBiosPayloadData.h in the specific silicon package
Additionally, DEBUG_VERBOSE message level is used for HeciCore.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This allows APL target to use the common HECI library.
The APL target uses the common HeciLib from CommonSocPkg,
and overrides MeChipsetLib for Apollake specific APIs.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Capsule Command support added for anti rollback
security version number. User can create command
in text file and create capsule with CMDI mode.
{ARBSVNCOMMIT}
Platform APIs would be invoked to do SVN
commit operations by useing HECI interfaces.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
- Created BaseIpcLib
- Sideband Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- IPC Interface picked from
tianocore/edk2-platforms
branch: devel-IntelAtomProcessorE3900
commit: 181f9e6c6ccde6e3fa62278b3a8b39cfb5844a7c
- Updated Stage1BBoardInitLib.C with a test function
Signed-off-by: Andrey Vinokurtsev <avinok@gmail.com>
This patch fixed OsLoader boot from SD card issue on Intel APL CRB
borads. The SD/eMMC library was updated to follow the proper sequence
for SD card. Also platform code was updated to detect SD card and
apply SD card power using proper GPIO pins.
It fixed#729.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds generic functionality to
process Flash descriptor lock. It follows
Capsule Firmware update flow and interface
is updated. Command (CMDI) interface is added
to GenCapsuleFirmware which takes file with
command as input.
Sample Command format in text file input,
{FLASHDESCLOCK}
{Command2}
{Command3}
Firmware update lib handler parses high level commands
Specific command process and functionlity would be
performed by platform specific libraries.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform
Signed-off-by: Guo Dong <guo.dong@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added required code flow to prepare to enable DMA
protection for APL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For APL, since VT-d is only enabled
in FspSiliconInit, it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
platform security discovery driver having bug it was wrongly doing
pointer arithmetic and causing memory overwrite. this may cause
intermittent fault.
Removing ZeroMem call since its not required, ACPI table is already
ZeroMem allocated from PSD aslc code.
Signed-off-by: Prakash Chandra <prakash1.chandra@intel.com>
Current code does not clear firmware update trigger incase
of failures like, capsule image not found or capsule image
authentication failed.
Code is modified to fix this issue. As part of this change,
EndFirmwareUpdate function is moved from platform code to
core firmwareupdate.c. EndFirmwareUpdate function will call
ClearFwUpdateTrigger and this will end firmware update.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added code to:
- Trigger FWU using sticky register in SBL Shell
- Detect FWU mode using combination of sticky register and state
machine
- Clear the trigger flag at the end of FWU
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch does the following
1) Enable triggering firmware update from OS
2) When firmware update mode is given control, state machine
is set to capsule processing and firmware update platform
specific trigger is cleared. State machine will be used
hereafter to track firmware update
3) Created CheckStateMachine method in BoardSupportLib.c to
check state machine to see if firmware update is in progress
and set boot mode to firmware update.
4) Removed CMOS way of triggering firmware update and wrote code
to use Over-Clocking WDT Scratchpad (OC_WDT_SCRATCH) bits for
triggering firmware update
5) Update shell fwupdate command to use OC_WDT_SCRATCH bits.
6) Removed extra reset during sbl firmware update
7) Removed reset after updating configuration data update
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
HASH_STORE_TABLE is updated and HASH_STORE_DATA is added
to provide info with variable length sizes. Usage bits would
notify for multiple component/key using the same hash.
These data structure would optimize the hash store size
in storage.
PcdHashStoreSize would define the size of Hash store
to allocate in bios bootup.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
This is a follow-up to the previous WOL commit. The previous
implementation is more LeafHill specific. This patch further
added configuration data to control how wake up signal is mapped
into each PCIE root port. And the ASL code has been adjusted to
utilize that info so that the code can be more generic for all
other platforms.
The current default configuration for PCIE wake signal is aligned
with LeafHill CRB board. For other borads, to enable it properly,
it is required to override the wake signal configuration using DLT.
Test has been done on LeafHill to do WOL with yocto image. It worked
as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SerialPortLib sets UART Scratch Register to a known value at the first
initialization to avoid unnecessary re-initialization afterward. But,
one of Windows driver(SIO) re-configures UART Registers while the Scratch
Register is preserved. As a result, SBL skips serial port initialization
after restarting from Windows.
Therefore, force to initialize Serial Port at Stage1A all the time simply.
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is an issue with Vbt.bin in MR5; MR6 has this fixed.
Test: compiles OK, boots Linux OK.
Signed-off-by: Ursula Maplehurst <ursula@kangatronix.co.uk>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch switched to use SerialPortLib in BootloaderCommonPkg for
QEMU and CFL platforms. For APL platform, it can also use this common
library. However, it has an optimized SerialPortLib with FIFO enabled.
So for APL, it still uses its SOC specific library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch used the common API GetTimeStampFrequency() to get CPU
TSC frequency instead of the original GetCpuTscFreqency(). As part
of it, all SOC specific instances for GetCpuTscFreqency() were
removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
Removing hard code in PrepareBuildComponentBin.py, so it could
support other platforms. And enhance its logic to support to
run in different places.
Moving repo and commit information to driver INF so this script
could reuse code to support different drivers.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Generate NHLT(Non HD audio Link Table) depending on CFGDATA
- Add HDA_CFG_DATA for HDA and NHLT
- Create NHLT depending on config data value
HdaLib is from edk2-platforms devel-IntelAtomProcessorE3900 branch.
- Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
- Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/
Include/Private/Library/DxeScHdaNhlt.h
Include/Private/Library/ScHdaLib.h
Include/Private/ScHdaEndpoints.h
Private/DxeScHdaLib/ScHdaEndpoints.c
Private/DxeScHdaLib/ScHdaLib.c
ScInit/Dxe/ScHda.c
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows to use one GPIO pin to select different Payload ID.
When enabled, if GEN_CFG_DATA.PayloadId is set to 'AUTO', the GPIO pin
low level will select OsLoader payload, and high level will select UEFI
payload. If GEN_CFG_DATA.PayloadId is set to other values, the GPIO pin
low level will always select OsLoader payload, and high level will
select the Payload ID specified by GEN_CFG_DATA.PayloadId.
On APL LeafHill, OxbowHill and JuniperHill boards, the current GPIO is
set to GP48 (Pin 10 on J6B2 connector). This GPIO pin should be used as
input signal, and can be reconfigured for alternative functions after
the Payload ID selection is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Necessary FSP header files(ex. Fsp*Upd.h) will be copied from FSP
release repo. Additionally, cfl target for WHL/CFL platforms will
verify minimum FSP version like apl target.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch utilizes information from FspBin.inf to checkout specific
tag from FSP repo and copy files to SBL source tree.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Cleaned up SpiFlashLib in APL platform, and move it into
BootloaderCommonPkg, so that other platform could reuse
this SpiFlashLib
Signed-off-by: Guo Dong <guo.dong@intel.com>
Add ACPI_ENABLED() to align with MEASURED_BOOT_ENABLED().
Update MEASURED_BOOT_ENABLED() by checking PcdMeasuredBootEnabled
firstly.
Update PlatformFeaturesInit () in stage1b to fix potential inconsistent.
Update other code for changes above.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Common MM_PCI_ADDRESS() provided PCI device BDF to PCIE MMIO base address.
So remove MmPciAddress() and MmPciBase () defined in platform and update
code to use MM_PCI_ADDRESS().
Add TO_PCI_LIB_ADDRESS() in common library.
Signed-off-by: Guo Dong <guo.dong@intel.com>
FileSystemLib provides generic interfaces to access file system and
its files as a abstraction of FatLib/ExtLib.
- Added CloseFileSystem
If there are opened files in a specific filesystem, those files
will be de-allocated in CloseFileSystem.
- Added OpenFile/GetFileSize/ReadFile/CloseFile
The ReadFile() does not allocate any memory for the file content.
The caller of OpenFile() MUST allocate necessary memory before
calling ReadFile().
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch will add support for updating multiple firmwares
using a single capsule image.
Following modifications are made for existing firmware update flow
1) Gather and validate capsule image
2) State Machine will be set to capsule processing state.
3) Signature of the capsule image is now stored in reserved region
During each reboot until the end of firmware update, stored signature
will be compared against the capsule image signature to make sure
capsule image is not modified until the end of firmware update.
4) Process Capsule image to gather firmware images
5) Each Firmware image information will be stored in reserved region
using FW_UPDATE_COMP_STATUS. Update pending will be marked to
update pending state indicating that this image is not processed.
6) Firmware update will use the reserved region comp structures starting
with the first image with update pending state, update the comp update
pending field to processing and applies the image. After the update, pending
field will be updated to Done and updates the status of the update in the
component structure and moves on to next image found.
7) After all the component structure in the reserved region updating pending
field are set to Done. Firmware update mode is exited.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Firmware update with latest code broke on APL platform.
This patch fixed#162 by:
- Corrected the HECI command response flag check
- Always read FWU state machine using SPI command instead memory map
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For APL, the board might need SMBUS communication to talk to some
devices, such as PMIC. This patch ported the SMBUS library from
open sourced EDK2 Minnowboard3. Basic test was done on LeafHill
CRB to read/write PMIC registers through SMBUS.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Build a new SMM info HOB to payload to report SMM info.
Add UEFI payload variable region into flash map.
TEST=Tested on LeafHill with UEFI payload.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Maurice Ma