CentOS live CD iso image has different path for grub.cfg file. It
also used "linuxefi" and "initrdefi" for keywords. This patch added
support for it. With this patch, verified it can boot to CentOS
live-cd on APL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL used AllocatePool to allocae space for Linux files
including Kernel and InitRd. However, since InitRd is required to
be aligned at page boundary, it needs to use AllocatePages instead.
This patch addressed this issue. It fixed#908.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Migrated to Azure Pipelines for SBL CI to align with EDK2 project.
This is an initial commit to enable basic check. Currently it will
verify patch format and QEMU GCC build and test.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For UEFI Linux boot, a new parameter was added into BOOT_PARAMS.
This patch added this parameter support so that ACPI base can
be passed directly to kernel.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL code will build pointers in E/F segment for ACPI
and SMBIOS table. On some platforms, E/F segment is not supported.
So a new configuration ENABLE_LEGACY_EF_SEG is added. When
it is enabled, SBL will not use legacy E/F segment memory.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In current SBL BootloaderCorePkg dsc and fdf files, it contains
hard-coded INF file path for SOC or board, such as ACPI INF
file and SOC/Board init library INF file. It makes it hard for
platform to provide its own overriding using different path.
This patch addressed this issue by allowing platform to override
the default paths in BoardConfig.py.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current FSP rebasing script SplitFspBin.py has support for both
PE32 and PE32+ image formats. However, while updating the ImageBase
field in the image header, it always assumed the ImageBase field is
32bit long. Since PE32+ image format defined ImageBase as 64bit,
the current script will only update the lower 32bit value and leave
the upper 32bit untouched. It does not work well for PE32+ image
that requires update in the upper 32bit ImageBase field. The
expected behavior is to update the full 64bit field. This patch
implemented this fix.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The calculation on where to start reading the
remainder of the boot image from is not being
calculated properly, the aligned header size
is given in bytes instead of in terms of block
size. This patch updates the calculation
accordingly.
Also, if SwPart is set as 255 then the LBA given
will be used as an absolute LBA instead of used
relative to the SwPart's starting LBA.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Use the default path only when MICROCODE_INF_FILE
is not defined in platform board. Currently it will
override the one defined in platform.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Microcode module locates in different place.
so each platform could specify the path by
MICROCODE_INF_FILE in BoardConfig.py.
By default, it uses the same path if there
is no MICROCODE_INF_FILE defined in platform.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* Enable frame pointers (via /Oy-) for 32-bit modules. From the
documentation: "If you specify a debug compiler option (/Z7, /Zi, /ZI),
we recommend that you specify the /Oy- option after any other
optimization compiler options."
* /O1b2s is equivaled to /O1 (/Ob2 and /Os are included in /O1)
* /Z7 for debug info is obsolete, replace with /Zi
Signed-off-by: Mircea Gherzan <mircea.gherzan@intel.com>
In 64-bit operation, some PCI devices have high mmio BARs,
but 32-bit FSP can only access 32-bit memory space.
This introduces and additional PCI resource downgrade option
to downgrade all PCI devices under Bus-0.
- self._PCI_ENUM_DOWNGRADE_BUS0 = 1
Force to have 32-bit BAR for all Bus-0 devices
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL build needs the actual FSP binary to pass the build.
This patch enables a mode to test the build without the actual FSP
bianry. It is useful for test before the FSP binary is available.
It is controlled by HAVE_FSP_BIN option. It can be overriden in
BoardConfig.py file.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch addressed an issue while detecting the
BOM ID for Upx platform which is causing the MRC
to fail.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This will report pcie config space region as a reserved memory in e820
and let Linux use the PCI MMCONFIG which has bus range information.
If it is not reserved, the pcie config space region will be freed/available
for PCI devices.
Signed-off-by: Aiden Park <aiden.park@intel.com>
GpioConvert Tool converts Gpio config data between following
sets of formats:
[.h, .csv, .txt] ---> [.yaml, .dlt] and vice-versa
.dsc related conversion is deprecated starting from this commit.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Using ConfigEditor to save back DLT changes, it will produce two
PlatformId lines in DLT file. This patch removed the extra line.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
o This is a common HECI PCI config space across platforms which
return STS6 space.
o HeciGetManufactureMode() returns if the platform is in debug mode
(fuses unlocked) or production (fuses locked).
Signed-off-by: Divneil Rai Wadhawan <divneil.r.wadhawan@intel.com>
Current ConfigEditor produces the same result for
"Save full cfg data" vs "save cfg changes". This patch provided
a fix for it. It fixed#882.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In ConfigEditor, while scrolling page using mouse middle wheel,
the Combo configuration items will change its default value. It
is because Combo control will bind MouseWheel event by default.
To address it, added code to unbind it explicitly.
It fixed#878.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed link error for APL NOOPT build due to compiler
intrinsics functions. However, due to APL hardware requirements,
it is not feasible to fit NOOPT build into real flash. This
patch will not fix the NOOPT build error caused by code size issue.
For example, the following error might still occur for APL NOOPT
build:
Invalid the required fv image size 0xe3b0 exceeds the set fv image
size 0x6000
The APL SOC requires Stage1A to fit into 32KB. Since FSP-T will take
8KB, it only gives 24KB for SBL Stage1A code. NOOPT build will create
about 56KB for Stage1A, and it is impossible to fit into the layout.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Check for Write access permission during
Write/Erase Flash cycles for BIOS/FLAHD regions.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Since SBL could be built into either x86 or x64 mode, and the payload
can also be x86 or x64 mode. When mixed modes are used, it is required
to switch to proper mode first before calling into payload entrypoint.
This patch added this check to switch to required mode before calling
into payload entry point.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch expanded HECI service to include send, receive and
reset interface functions. This helps in making firmwareupdatelib.c
and PSDlib common across platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This will fix the ucode repo checkout issue on 'cfl' target.
FYI, here are simple steps to reproduce.
1) Build 'apl' target first
2) Build 'cfl' target -> fails to checkout ucode repo
Signed-off-by: Aiden Park <aiden.park@intel.com>
During X64 enabling, there was a pending task to enable 32bit
MultiBoot support. It is not implemented. This patch added the
support to allow X64 SBL to boot a 32bit MB image through thunking.
As part of this patch, the ThunkLib is separated from the FspApiLib
so that it can be shared by other component.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The structure of ME_BIOS_PAYLOAD varies on silicons. So, it's moved to
silicon directory and common structures are in MeBiosPayloadDataCommon.h.
- MeBiosPayloadDataCommon.h in CommonSocPkg
- MeBiosPayloadData.h in the specific silicon package
Additionally, DEBUG_VERBOSE message level is used for HeciCore.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This allows APL target to use the common HECI library.
The APL target uses the common HeciLib from CommonSocPkg,
and overrides MeChipsetLib for Apollake specific APIs.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This allows CFL target to use the common HECI library as it is.
The CFL target uses both HeciLib and MeChipsetLib from CommonSocPkg,
and the unnecessary files are cleaned-up.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This adds a common HECI library for the same APIs on all platforms.
New MeChipsetLib is intruduced for the silicon specific HECI APIs.
- Silicon/CommonSocPkg/Library/HeciLib
- Silicon/CommonSocPkg/Library/MeChipsetLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
Different SoCs can use different versions of
Gen graphics and subsequently may use different
versions of the IGD Op Region; the OVER variable
will determine how the OS GFX driver interprets
the IGD Op Region provided in ACPI space.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Currently the build tool will always find FSP binaries from
Silicon'\self._board.SILICON_PKG_NAME\FspBin folder.
This patch enhance the build tool to support to get FSP from
_FSP_PATH_NAME. If _FSP_PATH_NAME is not specified, the default
behavior is same with current build.
If user wants to use a different one, they could override it
in BoardConfig.py as below:
self._FSP_PATH_NAME = 'Silicon/Fsp'
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added support to allow platform to add specific include
folders for the build. All include paths will be relative to the
SBL $(WORKSPACE).
To eanable this feature, please add similar definitions as below
into BoardConfig.py. For example,
self._EXTRA_INC_PATH = ['Silicon/QemuSocPkg/Include/Fsp']
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch did the following
1) Added common routines LocateVbtByImageId to look for VBT image using
ImageId provided by configuration data and GetVbtAddress.
2) GetVbtAddress routine will provide abstaction for all platforms
irrespective of multiple VBT or single VBT used by the platform.
3) LocateVbtByImageId routine is moved from platform local function to
common package.
4) VbtImageId configuration option defined in QEMU platform config is
moved to common configuration in CfgData_Common.yaml
5) ApolloLake VBT ID selection is now done using configuration data.
6) Added latest VBT binary for CFL, WHL is using existing VBT.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Currently SBL library has GetDeviceAddr() to get the device
address based on device type and instance. This patch adds
SetDeviceAddr() to update a given device type and address so
that platform could update the device table dynamically.
Signed-off-by: Guo Dong <guo.dong@intel.com>
The SATA and USB HwPart usage for BootOption
config data varies from the other block device
types. This patch adds clarification to explain
the meaning of HwPart for these 2 media types
respectively.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Maurice Ma