KW reported the expression 'Override->Table[Index].RevId'
can never reach the value '0xFFFF', where RevId is of type UINT8
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Add PchPseAicEnabled and PchUnlockGpioPads in
CfgData_Silicon.yaml file to allow modification
using Config Editor tool.
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Some of the RTCT table entries werent populated due to this
missing UPD setting. Hence, assigning it to the correct value.
TEST= Verified the fix on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch adds control option for TCO timer.
Use case: the control option shall be enabled when Linux hw watchdog
driver (iTCO) is enabled.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds "fs load" command to SBL shell so that it can be
used to load a file from boot media into memory. It also supports
loading file at specified memory address.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Universal Payload defined new HOBs for serial port information.
This patch switched to use the new hob instead of the old one to
retrieve serial port information.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds a MpServiceLib for payload so that a payload
can utilize this library to run tasks on specified processor.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Graphics driver in FSP Silicon init is expecting
board related changes for VBT, so moved UpdateVbt
function call before Silicon Init.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Removed RTC logic, it is problematic and should not be used,
all other platforms are not using this logic and
we should remove this from the code
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
CPU signature and ucode revision are ciritical info and should be
printed out as early as possible. This patch adds the info print
in SBL Stage1A.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL PCI enumeration does not allocate resource for PCI ROM
bar because SBL does not deal with option ROM at all. However, the
Linux kernel might expect the ROM bar resource to be allocated.
This patch introduces a static build configuration to allow support
PCI resource allocation for PCI ROM bar.
To enable this feature, please add following into the project
BoardConfig.py file:
self._PCI_ENUM_FLAG_ALLOC_ROM_BAR = 1
By default, it will be disabled to keep the same behavior as before.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
If there is DEBUG output during PCI enumeration, it could cause SBL
hang due to invalid PCI bar resource. In this case, SBL will force
to return 0 for any serial port register read. And it might cause
dead loop because of LSR_TXRDY bit polling in SerialPortWrite().
To avoid this potential dead loop, it is required to set LSR_TXRDY
bit for LSR_OFFSET register read if the PCI resource is invalid.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
According to PCI spec, it is required to check the multi-function
support in PCI configuration header type before scanning next PCI
function. Current SBL does not follow this, and it caused duplicated
PCI devices listed in Shell command "lspci". This patch fixed
this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current VBT patching uses a static big structure VBT_TABLE_DATA to
parse the VBT data. It is not reliable because the sub-structures
within VBT_TABLE_DATA might change between different revision. A
better solution is to look through each block data using the common
block header info. It can provide better back compatibility. This
patch implemented this.
It fixed#1504.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support for ADLN platform.
EC related ACPI changes need to be reinvestigated
as disabling ECAvailable NVS change might be
sufficient to disable EC support in ACPI.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch enables graphics console when entering FWU payload.
FWU progress will show on both graphics console and serial port.
Signed-off-by: kokweich <kok.wei.chan@intel.com>
This patch fixes the test case where when a bad dso is
provided, it will revert back to the default dso settings.
TEST= Ran the test case successfully on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
On TGL, Linux reported ACPI errors on missing PRES method for SATA
port 0. This patch added the missing PRES implementation for all
SATA ports.
This fixed#1497.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL ACPI table does not define any I2C pad or panel. And
it will cause ACPI error for Linux. This patch added conditional
scope for I2C pad and panel reference so that if pad type or panel
type is not defined, these scope will not be used by ACPI.
This fixed#1496.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Fix two errors:
ACPI Error: Aborting method \_SB.PR00.GCAP due to previous error
(AE_INVALID_TABLE_LENGTH)
ACPI Error: Aborting method \_SB.PR00._PDC due to previous error
(AE_INVALID_TABLE_LENGTH)
UEFI BIOS always does dynamic loading, but SBL does static loading
instead.
Signed-off-by: Randy Lin <randy.lin@intel.com>
As part of FSP updates for ADLPtest board, update
Silicon UPD settings.
TEST=Validated boot on the RVP board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Update the iasl version in Dockerfile to 20200925
Current iasl version in Dockerfile out-dated and
causing build error in Docker
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch added configuration array data size check to ensure it
is DWORD aligned. It will prevent some unexpected errors later on
while merging the configuration data.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
With latest changes for S0ix, PciePm is expecting GetCpuSku and
GetCpuSkuInfo function declaration in header files. Added these
declarations in CpuPcieHsPhyInitLib header file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-S.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for ADL.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
This patch enable S0ix feature in ADLP
1. Ported correct NVS value for ADLP.
2. Ported ACPI value refer to BIOS.
3. Implemented workaround for RP08.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Current TGL platform set 0 as the PCI end bus number in ACPI
MCFG table. And it caused incorrect MMCONFIG range calculation in
Linux. This patch updated the template to use 0xFF as the PCI
end bus number.
It should fix#1481, to be confirmed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-s.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for TGL.
Verified: TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
When enable TGL IBECC, the IbeccProtectedRegionMask should be visible
too in the Config Editor but its not happening this way.
Signed-off-by: Randy Lin <randy.lin@intel.com>
This patch extended the LZ4 library to support both compression and
decompression. It is useful for SBL to support runtime compression
in order to reduce data size. It is in sync with the LZ4 1.7.4 used
in the BaseTools.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch updated python version to be 3.8.x for Azure Pipelines.
Without this change, the Azure Pipeline build will fail.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds Platform and Silicon support for Alderlake
project. Currently, FSP and microcode are not publicly
available. So build will fail with errors. We will update
the project whenever they are available.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
s0ix feature enabling flag also turn off some FSP configs
so that default SBL image can't detect the onboard Lan
and type c devices.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Is is reported that SBL QEMU target crashes when running in nested
virtualization env. For example, run QEMU with KVM flag inside
Ubuntu running on Windows Virtual Box.
After debug, it turned out somehow the KVM generated exception for
instruction "movd mm0, eax" at the very beginning. This was used to
save the CPU BIST info. If it is moved to be after switching to FLAT32
mode, then everything goes well. This patch moved the BIST saving
into later stage in the boot in order to address the KVM crash issue.
This fixed#1469.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Remove FSP headers due to the FSP download script
will check if FSP header exist. It will only replace
if there is no existing FSP headers.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch enhanced GPIO convert tool so that it can handle the
new GPIO template format.
EX:
To convert GPIO from YAML format to CSV format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
Platform\ElkhartlakeBoardPkg\CfgData\CfgData_Gpio.yaml
-of csv -o gpio.csv
To convert GPIO from CSV to YAML format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
gpio.csv -of yaml -o gpio.yaml -t new
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes no activity on UART0 pins when enabling it for serial
communication.
In TGL, there are two UART0 instances (GPP_C8~C11 and GPP_F0~F4) while
one (GPP_F0~F4) is shared with CNVI. This patch enables GPP_C8~C11 as
the UART0 instance to reduce the conflict with CNVI.
This patch also fixes the GPIO pins definition for TGL-H and moves
serial io initialization code to SerialIo.c to simplfy Stage2BoardInitLib.c.
Test: TGL-UP3 RVP and TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Vincent Chen