In X64 mode, current stage unmapping implementation does not
restore the original identical address mapping. It will cause
issue in some condition. This patch fixed this unmapping issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL does not provide CFGDATA to change the current boot
option although it can be done in SBL shell. This patch added this
into CFGDATA so that it can changed using board CFGDATA. A special
option AUTO is introduced to indicate the priority between CFGDATA
and board specific overriding. When AUTO is selected, board specific
overriding should be used. Otherwise, CFGDATA should be used for
CurrentBoot option.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will fix stage transition failures for X64 targets built with gcc
which is caused by mis-matched EFIAPI calling convention.
- Add EFIAPI to STAGE_ENTRY interface for Stage1A -> Stage1B
- Add EFIAPI to PAYLOAD_ENTRY interface for Stage2->OsLoader Payload
- Remove unused KERNEL_ENTRY interface
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch ported the X64 ASM code from the latest IPP github repo.
All 4 algorithms have been tested.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted the Stage1A heap size and OsLoader size to
satisfy CFL build and boot requirment. This has been tested on
UPX board. It has dependeny on preivous PR #636.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled APL X64 boot. In X64 mode, more heap is required
for Stage1A since it needs to build page tables. As part of it, APL
CAR region map has been re-arranged so as to save more space. This
has been tested on LeafHill CRB board.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In certain condition, the FspTempRamExit() API will be executed from
CAR. If so, the thunk call itself cannot be in CAR otherwise the
call will hang immediately after the CAR teardown. To resolve it,
the thunk call needs to be copied over to memory before calling the
FspTempRamExit() API. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current build only allows board to customize the DSC libraries.
It is better to allow more flexible DSC customization. This patch
enabled this capability. Board can override library, PCDs, etc.
As part of it, the old GetDscLibrary() interface will be deprecated.
Please use GetPlatformDsc() instead.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since Python 2.x is EOL'd we should all be
transitioning over to use Python 3.6+. For
information on the latest versions of tools
see the Slim Bootloader documentation:
https://slimbootloader.github.io/getting-started/build-host-setup.html
Signed-off-by: James Gutbub <james.gutbub@intel.com>
After merging back x64 support, UEFI payload loading starts to fail
with SBL. It is due to the pointer was not properly initialized
for the component loading. This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable Stage1A boot in X64 mode
This patch added necessary changes to enable QEMU boot through
Stage1A in SBL X64 build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable QEMU Linux boot in X64 mode
This patch enabled SBL X64 boot for Linux. At this moment, since
FSP is still in 32 bit mode, it is required to thunk back into
32 bit mode to call FSP APIs.
It fixed#622.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Due to missing normal function implementations in some x64 code, GCC
optimized many code off from the final image which caused synbol
patching issue later on. This patch fixed this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Add missing X64 MdePkg Library
This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Make X64 target buildable
This is just to build X64 target - Not functional.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This an initial patch to add x64 build for SBL. A new build flag
'-x64' is added to indicate x64 arch build. This cannot be fully
used at this moment because it has many dependencies on other x64
libraries. Only VTF reset vector x64 build is tested.
VTF x64 flow is different from IA32. It switches to 32 bit
mode as usual and then calls into FspTempRamInit to set up CAR.
Once CAR is ready, it builds 4GB identical mapping page table for
x64 and then switches to x64 long mode. Finally, it locates the
STAGE1A entry point and tranfers the control to STAGE1A in pure
64 bit mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are lots of common code in Stage1A/1B/2, so it makes sense
to put those into a StageLib so that the same code can be reused.
As part of it, PagingLib is also restructured to align with Stage
mapping/remapping. It will consider both X64 mode and IA32 mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL used AllocatePool for IAS image or container image
loading. It is not ideal since some file, such as InitRD, requires
page aligned address. It is better to use AllocatePages to allocate
the buffer instead. This patch fixed this.
It fixed#627.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This supports XCODE toolchain in Mac OS.
- Tested on macOS Catalina version 10.15.2
- Tested with Apple clang version 11
- Verified QEMU target
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added UP2 board memory SKU3 support. This was enabled
by trying different memory configurations to find the working
configurations. It might not be optimal, but a good start point.
Special acknowlegement to andreyv1978 who did the enabling on his
board and contributed the code back.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In SBL dsc/fdf file, PLATFORM_PACKAGE was defined. But it is actually
BootlaoderCorePkg. It is confusing. Instead, it can be just removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add SMI status register
Add SMI lock register
Add REG_TYPE_MMIO register type
Zero SMM HOB
Fill SMI lock info for CFL and APL platform
Signed-off-by: Guo Dong <guo.dong@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
When multiple USB mass storage boot devices are connected, current
SBL will only boot from the 1st one enumerated by the USB bus. This
patch added support to boot from the remaining devices. This feature
will be controlled by PcdMultiUsbBootDeviceEnabled. And it can be
overridden by board using ENABLE_MULTI_USB_BOOT_DEV. When it is enabled
for USB block IO interface, the hardware partition in boot option
will be used to indicate the index of the USB mass storage devvice.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch opitmized GDT loading in different stages. The old code
put GDT in code segment so it needs to be relocated every time when
code relocation/remapping occurs. By putting GDT into heap, it avoids
the GDT reloading. It only needs to be done twice, PreMem and PostMem.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This is a regression on the grub.cfg file parsing. When parsing
each menu entry in grub.cfg, the index should not be advanced
at the end. It will cause the boot index shift by 1 if doing so.
This patch fixed this issue. Tested with Ubuntu boot.
It fixed issue #606.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added subregion value output into full delta file so
that it is easier to update the value directly intead of fields.
For example, the new GPIO output in delta will be:
## GPIO_CFG_DATA.GpioPinConfig0_GPP_A00 | 0x350A581
GPIO_CFG_DATA.GpioPinConfig0_GPP_A00.GPIOPADMode_GPP_A00 | 0x1
This 1st comment line is newly added by the patch.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed incorrect GPIO config for A07 on UP Xtreme board.
SBL configured GPIO A7 as native function 1 (PIRQA). However, the
board used it as an output control pin. The incorrect configuration
caused kernel interrupt issue reported by issue #603. This patch
fixed issue #603.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
USB2 port 8 (index 7) is connected to MCU on UPX board. It does not
respond to USB enumeration. The original code disabled port 10, but
it should be port 8. This patch fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed incorrect GPIO pin used for BOM ID detection for
UPX board. It also fixed the incorrect RX bit within GPIO CFG DW0.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added required code flow to prepare to enable DMA
protection for CFL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For CFL, VT-d PMR cannot be fully enabled
before FspSiliconInit. So it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added required code flow to prepare to enable DMA
protection for APL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For APL, since VT-d is only enabled
in FspSiliconInit, it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch synced up to the latest EDKII XHCI library and then
added support for IoMmu interfaces. This will allow the library
to use DMA buffer for I/O transactions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added IoMmu interfaces support for MMC library. This will
allow the eMMC library to use DMA buffer for I/O transactions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support for IoMmu interfaces. It will allow the
library to use DMA buffer for I/O transactions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added IoMmu support for NVMe block access library.
This will allow the library to use DMA buffer for I/O transactions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added IoMmu interfaces support for UFS library. It will
allow the library to use DMA buffer for I/O transactions.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
As part of the DMA memory protection, it needs API to enable/disable
DMA protection. This patch simplified the API to do that using
SetDmaProtection().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added DMA memory type into memory allocation pool for payloads.
This DMA memory buffer with PcdDmaBufferSize is located at address
aligned at PcdDmaBufferAlignment after Payload reserved memory. Memory
type EfiRuntimeServicesData is used to indicate DMA memory type.
Stage1B calculates the DMA memory location using fixed PCDs so that
platform can set up DMA protection as early as possible after memory is
ready. In Stage1B or Stage2 platform code should use platform VTd
information to setup PMR to protect all low memory except for the DMA
buffer range. DMA memory will be added into memory pool at the entry
point of the payload. Before transfering to OS, the DMA memory protection
can be disabled, and the DMA memory pool can be reclaimed for OS usage.
Currently only boot media device will utilize the DMA buffer range for
block access operations. So it should only be required by payloads. GFX,
when enabled, will also use DMA. It will be targeted to the system stolen
memory which is not protected by PMR.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
By default 4MB was allocatd for OS crash mode support. Hoever, no
project is really using it at all. The default should be changed
not to reserve any memory for it. For platform needs it, it can
override using platform specific CFGDATA.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Maurice Ma