The patch fixes SIO UART in COM mode by providing Acpi Gns
correct values.
Test method: grep 16550A /proc/tty/driver/serial
If a SIO UART run in COM mode, its MMIO should be in
FE020000 ~ FE035FFF (EHL serial IO in ACPI mode).
Verfiied: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Universal paayload hobs are updated for secure boot
and measured boot. Event logs Hobs are created to consume
by TCG2Dxe in uefi payload.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Change USB4 CM Mode to 0. This value is consumed by FSP and UEFI BIOS but not by SBL.
Different setting causes issue with TBT device in Windows which might result in CATERR.
Tested to boot Windows and Yocto.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Added new platform ID for RPLP DDR5 CRB (COM-HPC board). This board has
no EC or board ID FRU, but it is so far the only board in the ADL/RPL
family like this so it is used as a board identification criterion.
Added DdiConfig table as well.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Resolve the build break when remove the O1b2 CC flag.
error LNK2001: unresolved external symbol __allshl
Signed-off-by: Randy Lin <randy.lin@intel.com>
Signed-off-by: Randy Lin <randy.lin@intel.com>
MemTestOnWarmBoot UPD added into Config Editor. This UPD is enabled to ensure Base Memory Test is running in SBL.
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
Plaform is halted when TPM is not detected.TPM support is
enabled with BTG 0 and boot halted when PTT is not enabled
in straps.
TPM should be able to boot when TPM is not present and this
patch fixes this issue.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Argument DataLen of function InternalGetVariable() inside Reclaim()
function is not initialized. This uninitialized value is assigned
to another variable and compared, resulting in EFI_BUFFER_TOO_SMALL
error when Data is NULL. Hence added Data NULL conditional check with
DataLen to overcome EFI_BUFFER_TOO_SMALL error when Data is NULL.
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Create a tool that corrupts SBL components so that
the SBL resiliency feature can more easily be tested
and demonstrated
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Implement a function to support FIPS mode enablement in ADL
Test: Booted with Windows and Yocto
Verified with FIPS enablement support in ADLN
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Updated the GPIO shell command to take GPIO group and pin number as inputs.
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
CFGDATA regions (each CFG tag) needs to be 4-byte aligned since this
CFGDATA header field uses the low two bytes of the length for ConditionNum.
Without this change, unaligned CFG region yaml files will cause a build
error and need to be manually padded. This change adds a field "__reserved"
to each CFG structure that requires padding.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Much like the corresponding Stage1A patch, this patch aligns the
Ia32 Stage1B and Stage2 stacks to 16 bytes, like what is already the
case for X64, so that we follow Version 1.0 of the System V Intel386
ABI supplement, and satisfy any expectations our compiler may have
regarding stack alignment.
A nice side effect of this change is that it allows building an Ia32
Slimbootloader with -msse which can run on real hardware, which requires
16-byte stack alignment. Slimbootloader currently already enables SSE
in XCR0 early on in Stage1A, and it has SSE versions of various helper
functions written in assembly, in other words, it already makes use of
SSE, but allowing the compiler to emit SSE instructions requires 16-byte
stack alignment, because access to unaligned on-stack SSE variables
will throw #GP on real hardware. (QEMU doesn't seem to enforce the
requirement for natural alignment of SSE memory arguments.)
Suggested-by: Peter Edwards <peadar@arista.com>
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
Updated FSP-M and FSP-S parameters to match with BIOS
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Added M.2 related PlatformNvs GPIO value for CRB board
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
If Payload Id is read from generic config data then
set Payload Id of LINX Payload to 0.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
Include TCC specific code inside TCC feature flag to avoid
build issues on unsupported platforms.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Check EC UPD flag prior to publish ECDT table and send EC cmd.
On Ecless board, EC ACPI object will not be invoked.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
library
Migrates FW resiliency APIs of Stage1B.c to
FirmwareResiliencyLib
Migrates FW update status types from FirmwareUpdateLib.h and
BootloaderCommonLib.h to FirmwareUpdateStatus.h
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
If TS bit flipped and it does not match FWU state,
assume ACM detected corruption in SG1A or SG1B and
recover broken BP
Add WDT trigger for recovery
Add ADL-specific WDT trigger for TS
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
TPM is intialized by ACM with profiles 3 & 5.
This patch enables the TPM in bootloader when boot guard
is not enabled. HAVE_MEASURED_BOOT in platform
board config controls the TPM in SBL.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Added UPD Ddr4OneDpc in DLT file and removed hard coded value.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Add the hard-coded GPIO table to the header file for reference purposes.
This table is currently part of the configuration.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
KM,BPM,ACM SVN are not commit at EOM.
End user has to perform this commit by doing
FwUpdate CMDI mode for ARB SVN commit.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Without initializing CPU fan control, EC will stop CPU fan after default
timeout. This patch initializes CPU fan control and fail safe control.
Some scenarios are related to the case: (1) bootloader shell;
(2) unexpected hang; (3) OS with no ACPI support; and (4) OS fails to
load ACPI driver
Test methods:
1. monitor CPU fan under SBL / UEFI Payload shell: expect non-stop
2. check CPU fan status after Linux starts: expect ACPI controls it
Verified: TGL RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
1. Update BoardID and PlatformID for CRB board
2. Direct return after read board id from smbus to avoid boardid clashing
3. Added ddi config for CRB board
4. Update FSPM UPD due to common value across all sku
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Adds a null check before dereference of a pointer
in the FW recovery flow
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This change makes sure that, during each recovery,
the FW update status structure is cleared and
repopulated
Without this change, in the event that there is
a full recovery and then an interrupted recovery,
the interrupted recovery is unable to resume
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This change removes a write of the FWU state
machine flag during the recovery flow
as the exact same write occurs later on
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This change accounts for the automatic mapping of
the TS region addresses within the recovery flow
Before this, the TS region would not get updated
during a recovery
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This change defaults to BP0 whenever the
BP cannot be determined instead of halting
the CPU altogether
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
stanley