HECI interface for getting extended support license period.
Efi test is added to call the EPS API for validation.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Config data uses comma ',' instead of dot '.' as the option separator.
Fix a typo in IehMode option which would cause ConfigEditor.py error.
Signed-off-by: Guo Dong <guo.dong@intel.com>
FSP 2.4 adds a requirement for Bootloader to respond to FSP Variable
requests in a way that is similar to UEFI variable services. This
implementation adds support for using the updated SBL VariableLib so that
the FspVariableServicesLib wrapper is no longer needed.
Additionally, support for Multi-Phase mem and SI init is added. FSP 2.4
introduces the mandatory MultiPhaseMemInit call, and makes the
MultiPhaseSiInit call mandatory where it was previously optional.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
EHL FSP does not send EOP (End Of Post) message at the
Ready to Boot. The patch adds support for SBL to send
the EOP during Ready to Boot.
Verified: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
It was not easy to figure out from boot log whether TSN
components are loaded successfully or not. Add debug prints
to indicate the loading status.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- MC and CMF Parity combined into one FSP UPD.
- Added SBL Config items for IehMode, TCSS D3Hot and D3Cold, CPU PCIe
Power gating, VccSt, TCSS Cstate limit. These are all needed for the FuSa
specific dlt file. ADL-S dlt files updated so D3Hot and VccSt defaults are
unchanged, since these defaults were previously set by PCH sku.
- FuSa diagnostic mode PCD to track Diagnostic mode across stages. Crash
Log Data PCD will not be used and has been removed.
- GSPI example driver header file added.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
A GPIO YAML can refer to any platform's GPIO table as
the base GPIO table. Since SBL supports upto 32 platform
IDs, the number for the check in the if condition should
be 32.
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Adds SBL boot performance data (Stage1 time, Stage 2 time, OsLoader time)
to the FPDT with type 0x3000 (Reserved for platform firmware Vendor usage)
Other fixes:
- Move logging of measure point 40F0 inside the condition for measured boot
- Add missing call to log measure point 40E0 used to log kernel setup print
time
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Saved timeout from reading EC. Reduced time up to 300ms.
Adjusted Stage 1A & 1B region size for ADLN Fastboot feature.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Reset EC available flag to 0 in dlt file.
Resolved ACPI Errors from dmesg log that point to EC Hardware.
Tested booting up Ubuntu and Windows.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
When UEFI Payload exists, SBL splits BIOS region into two
flash protected ranges, PR0 and PR1, by excluding UVAR (UEFI Var)
component.
Because ADL SPI controller supports 64KB maximum Erase Block Size,
current flash layout will result into 2 faults without the patch:
Fault 1: the size of PR0 and PR1 are not 64KB aligned,
Fault 2: the base address of PR1 is not 64KB aligned.
The patch updates REDUNDANT_SIZE to make sure it is 64KB aligned
and moves UVAR as the 1st region in non-redundant region.
Because (1) TOP_SWAP_SIZE, (2) SLIMBOOTLOADER_SIZE and (3)
UEFI_VARIABLE_SIZE (when payload exists) are already 64KB aligned,
it will be 64KB aligned after moving UVAR to the 1st region of
non-redudant region.
Verified: ADL-P RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Currently there are only few use cases for the lite variable.
FSP2.4 requires bootloader to have variable support. To avoid
creating a new variable instance, just update lite variable to
align with FSP 2.4 variable requirements.
Signed-off-by: Guo Dong <guo.dong@intel.com>
1.Build script will not copy FSP, VBT and Microcode bin files from repository
if it finds these files existing in taget folders.
Above step keeps them from unintentional update in series of build process.
Adding a board name to clean command helps to get latest binaries from repository
in next build.
2.Ignore empty board name from loading BoardConfig*.py
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Since OsLoader will never be exercised on S3 resume, there
is no need to check if boot mode is S3 resume before logging
TPM events in OsLoader
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This change ensures that consistent APIs are called to
determine if a hash gets extended to TPM PCRs
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Test config on CRB:
Set PchHdaEnable=1 in CfgData_GpuConfig.yaml
Linux OS, test by speaker-test -c 2 -D hw:0,7
Signed-off-by: Randy <randy.lin@intel.com>
This change only sets the GFX framebuffer cache type to Write-combining
when not booting the UEFI payload. The UEFI payload PCI hostbridge driver
will override the WC setting anways for the whole PCI root bridge memory
range, so it wasn't gaining the write-combining performance bonus, and was
causing a CPU exception in this particular case for RPL-P.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
platforms
Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file
Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
platforms
Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file
Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.
Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Update copyright years
Initialize pointers to NULL
Check pointers for NULL before de-reference
Standardize debug logs
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
* [ADL] Update TPM event logging to match BIOS
If measured boot disabled via BtG profile but enabled via SBL
config flag, skip logging startup locality TPM event
If measured boot enabled via BtG profile or SBL config flag, log
CRTM version TPM event
Set startup locality based off startup locality on ACM policy status
Log detail and authority PCR events based off SCTRM status on ACM
policy status
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
* Initialize startup locality and remove measured boot check
Initialize startup locality variable used in setting up event
log
Remove measured boot check as it is not seen in BIOS and it
occurs at higher level
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
---------
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This Patch add the support to set UFS clock frequency.
- Added the function to read or write specified attribute of a UFS device
- Shifted function which switch the link power mode and gear after ref_clock setting
because if an unsuported clock frequency being set, it won't be able to overwrite
the corrupted UFS attributes.
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
New CrashLog support design is for FSP to collect CrashLog info and report
in HOB. Bootloader responsibility is just to populate ACPI BERT with FSP
collected CrashLog Data now. That way bootloader has no Silicon code.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When building HelloWorld, it would build failure since SBL core
package is missing in PayloadPkg.dsc since
In general, the payload should not depend on BootloaderCorePkg.
Currently PcdAcpiEnabled is used in the payload entry module and
it is defined in the BootloaderCorePkg. This patch updates the
code to remove the dependency.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
ADL boards come with emmc as an in-built boot media.
Add EMMC option in the default list in order for the OS to boot
up when using OS loader payload.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
The PCH decodes MMIO accesses to the top of 4GB to SPI flash for a maximum
window size of 16MB. For SBL images larger than 16MB, this PostTempRamInit
hook was causing the MTRR to overlap with NEM stack set up by FSP-T,
causing a hang.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Add support for Up Xtreme i12 ADLP based board.
The PCIe M.2 slot CN12 on the board is able to detect NVMe SSD.
Debug output is enabled at header CN9 on the board(e.g. UART1)
Tested to boot with OS loader payload and UEFI payload.
To stitch the SlimBootloader.bin with IFWI uses StitchLoader.py script with '-p' as given below:
python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/adlp/SlimBootloader.bin -o sbl_upx12_ifwi.bin -p 0xAA000104
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Subash Lakkimsetti