* Create tool to generate uCode outside of full SBL build
Create a standalone tool that generates a full
uCode region binary separate from a full SBL build
This tool will be used to generate a uCode region
binary for incorporation into a FWU capsule
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
* Make region size optional parameter in uCode utility
When region size not is given explicitly to the uCode
utility, it aligns the combined uCode binaries up
to the nearest multiple of 4KB
The uCode utility also checks slot size and region size
are not exceeded
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
* Remove region size argument on uCode utility
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Currently SBL would return when preferred graphics mode is set
in the multiboot image. This patch would continue boot and print
the preferred graphics mode information.
Signed-off-by: Guo Dong <guo.dong@intel.com>
It was noticed that, if there is an error
updating a redundant component on BP1, it
gets retried on BP0
This change prevents that retry from happening as
identical boot partitions are desired
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Currently, only a single redundant SBL component, the configuration data
component, is allowed per update session. However, with support added for
ACM and uCode component updates, the user might desire to update multiple
redundant SBL components in the same session. This change allows this to
happen.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Currently, Slim Bootloader support for multiple VBT files doesn't work on EHL.
Support for multiple VBT files, which works on other platform, does not work
correctly for EHL. However, this change can fix it locally by adding the support
from another platform into the EHL support once integrated into the public SBL
Signed-off-by: ldevathu <linggeis.daran.devathurai@intel.com>
Fix two errors that prevent building QEMU SBL with the debug FSP on Linux:
- 0001-Build-QEMU-FSP-2.0-binaries.patch adds a variable "RegMask8" to
FspmInitEntryPoint() that is written but not read; GCC treats this as
an error;
- the resulting STAGE2 binary is larger than the 0x18000 bytes allocated
for it.
Signed-off-by: Bruno Achauer <bruno.achauer@intel.com>
RPL-P and ADL-P RVPs are essentially identical except for BoardID FRU.
Both need to work with SBL with RPL-P Silicon. To avoid duplicating
config data, this change will treat both as the same board.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
TCO timer could be enabled regardless resiliency feature.
So just remove the resiliency conditional.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
Before this change, whenever SG02 is corrupted
in both BP0 and BP1, SBL will continuously loop
trying to recover BP0 via BP1 and vice versa
This change makes it so that, if a failure is
detected on a recovery flow, the CPU halts
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Adds build-time PCD that hides corruptcomp
tool by default
Renames corruptcomponent to corruptcomp
Enhances error checking/logs
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Create a tool that corrupts SBL components so that
the SBL resiliency feature can more easily be tested
and demonstrated
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
While iterating over a USB descriptor in GetExpectedDescriptor(),
the "Len" variable always uses the 1st byte in the buffer,
This is only true for the 1st iteration, thereafter the variable should
advance as the descriptor advances.
Signed-off-by: Leon Theunissen <leon.theunissen@etion.co.za>
- update FSP version to MR5 FSP (09.04.30.51)
- update microcode version to 17
- update platform version to 1.5
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
During the build process, SG1A is built
for BP0 and a copy is made for BP1. Then,
the parameters of the BP1 SG1A are adjusted
to reflect that it is in BP1. One of the
parameters that gets adjusted during this
process is the uCode base. It was noticed
that this uCode base does not get updated
at all for platforms using FSP spec 2.2, but
another parameter gets updated instead.
Specifically, the error is in the FSP-T UPD
struct. The offset of the uCode base in
the FSP-T UPD struct is 0x40 for platforms using
FSP spec 2.2. However, the offset that actually
gets updated for platforms using FSP spec 2.2 is
0x20. This change corrects this offset for the
relevant platforms.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
PcdTccEnabled was declared as a FeaturePcd which evaluates to a code symbol
and can't be used in a #if. From the preprocessor perspective it is always
undefined. Changed this pcd to a FixedPcd instead.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
The patch fixes SIO UART in COM mode by providing Acpi Gns
correct values.
Test method: grep 16550A /proc/tty/driver/serial
If a SIO UART run in COM mode, its MMIO should be in
FE020000 ~ FE035FFF (EHL serial IO in ACPI mode).
Verfiied: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Universal paayload hobs are updated for secure boot
and measured boot. Event logs Hobs are created to consume
by TCG2Dxe in uefi payload.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Change USB4 CM Mode to 0. This value is consumed by FSP and UEFI BIOS but not by SBL.
Different setting causes issue with TBT device in Windows which might result in CATERR.
Tested to boot Windows and Yocto.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Added new platform ID for RPLP DDR5 CRB (COM-HPC board). This board has
no EC or board ID FRU, but it is so far the only board in the ADL/RPL
family like this so it is used as a board identification criterion.
Added DdiConfig table as well.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Resolve the build break when remove the O1b2 CC flag.
error LNK2001: unresolved external symbol __allshl
Signed-off-by: Randy Lin <randy.lin@intel.com>
Signed-off-by: Randy Lin <randy.lin@intel.com>
MemTestOnWarmBoot UPD added into Config Editor. This UPD is enabled to ensure Base Memory Test is running in SBL.
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
Plaform is halted when TPM is not detected.TPM support is
enabled with BTG 0 and boot halted when PTT is not enabled
in straps.
TPM should be able to boot when TPM is not present and this
patch fixes this issue.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Argument DataLen of function InternalGetVariable() inside Reclaim()
function is not initialized. This uninitialized value is assigned
to another variable and compared, resulting in EFI_BUFFER_TOO_SMALL
error when Data is NULL. Hence added Data NULL conditional check with
DataLen to overcome EFI_BUFFER_TOO_SMALL error when Data is NULL.
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Create a tool that corrupts SBL components so that
the SBL resiliency feature can more easily be tested
and demonstrated
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Implement a function to support FIPS mode enablement in ADL
Test: Booted with Windows and Yocto
Verified with FIPS enablement support in ADLN
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Updated the GPIO shell command to take GPIO group and pin number as inputs.
Signed-off-by: M Karuppasamy <karuppasamy.m@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
CFGDATA regions (each CFG tag) needs to be 4-byte aligned since this
CFGDATA header field uses the low two bytes of the length for ConditionNum.
Without this change, unaligned CFG region yaml files will cause a build
error and need to be manually padded. This change adds a field "__reserved"
to each CFG structure that requires padding.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Much like the corresponding Stage1A patch, this patch aligns the
Ia32 Stage1B and Stage2 stacks to 16 bytes, like what is already the
case for X64, so that we follow Version 1.0 of the System V Intel386
ABI supplement, and satisfy any expectations our compiler may have
regarding stack alignment.
A nice side effect of this change is that it allows building an Ia32
Slimbootloader with -msse which can run on real hardware, which requires
16-byte stack alignment. Slimbootloader currently already enables SSE
in XCR0 early on in Stage1A, and it has SSE versions of various helper
functions written in assembly, in other words, it already makes use of
SSE, but allowing the compiler to emit SSE instructions requires 16-byte
stack alignment, because access to unaligned on-stack SSE variables
will throw #GP on real hardware. (QEMU doesn't seem to enforce the
requirement for natural alignment of SSE memory arguments.)
Suggested-by: Peter Edwards <peadar@arista.com>
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
Updated FSP-M and FSP-S parameters to match with BIOS
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
Added M.2 related PlatformNvs GPIO value for CRB board
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
If Payload Id is read from generic config data then
set Payload Id of LINX Payload to 0.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
Include TCC specific code inside TCC feature flag to avoid
build issues on unsupported platforms.
Signed-off-by: Akshatha Thekkade <akshatha.thekkade@intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat@intel.com>
Check EC UPD flag prior to publish ECDT table and send EC cmd.
On Ecless board, EC ACPI object will not be invoked.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Lennert Buytenhek