Removed the source code related to TCC tools
including DSO switch, SWSRAM switch, TCC subregions
TCC Error Log switch, RTCM, RTCT
The code change applies on TGL/EHL/ADL/RPL/MTL
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
* fix: [ADLN] Prevent to enumerate RP25 and above
PCIe RP25 and above are supported only when PCH seriese is PCH S.
Prevent to enumerate RP25 and above to address resource conflict with eMMC.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
* fix: [ADLN] Update eMMC driver strength
Update eMMC driver strength 40Ohm for CRB.
Improve performance benchmark result.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
---------
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
The debug fsp report:
SDI#0: No matching HD-Audio codec verb table found for codec (0x10EC0897).
fix and can see
SDI#0: Detected HD-Audio Codec 0x10EC0897 rev 0x04
Found Verb Table for VendorID 0x10EC, DeviceId 0x0897, RevisionID 0xFF (SDI:FF, size: 4 dwords)
Verified on MCL
Signed-off-by: Randy <randy.lin@intel.com>
Update the option for RVP & LP5 while stitching, add "-o rvp" or "-o lp5" at the end of command
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
The "Allow this device to wake the computer" option
(Device Manager => Network adaptors => Properties of PCH GbE
=> Power Management) is grayed out in Windows.
Added the "_PRW" ACPI method to enable the feature.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
The PLATFORM_{NAME} macro is dynamically defined by BuildUtility.py, which
is based on the board file name. Since ASL has been merged into ADL-N, the
PLATFORM_ASL macro has become obsolete and is no longer valid. This commit
removes all instances of the deprecated PLATFORM_ASL.
Additionally, this commit addresses an issue where PLATFORM_ADLN was not
defined in Stage1ABoardInitLib.c during the build process for ADL-N. The cause
was that ConfigDataStruct.h was not included.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch adjusted MTRR settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used or Fast Boot is enabled.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Check EC device existence before sending command.
The patch prevents waiting for timeout when reading BoardId.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
The FSP UPD code region should try to cover SBL Stage1A and Stage1B
with a minimum region size. It would impact MTRR settings before memory
init and the MTRR settings would be updated after FspTempRamExit().
Reduce the code region size could improve boot performance for some
SKUs.
Signed-off-by: Guo Dong <guo.dong@intel.com>
BiosRedAssistance setting is added to stitch config.
By default it is disabled. Enable for FW resiliancy.
Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
Accidental removal of EFIAPI from CalculateRelativePower function in
Stage2BoardInitLib.c caused GCC to issue incompatible-pointer-types error.
This patch addresses the build issue.
Signed-off-by: Ong Ee Lim <ee.lim.ong@intel.com>
Issue: fsp debug log goes to EC port on RVP.
This fix also require FSP update to BIOS version 4053_51 or newer.
Signed-off-by: Randy <randy.lin@intel.com>
FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
- Update Common MeChipsetLib to account for ARLS Me Bus.
Now,the bus number comes from Platform code:
if ARLS bus = 0x80, else bus = 0x0
- Update Heci Pci read calls in HeciMeExtLib to account for
both ARLS and ARL U/H BDF differences.
- Delete ARL specific MeChipset header files as it now uses
common header files from Common Package.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
S0ix failed when NVME attached due to incorrect PCI device configuration
Ported RootPortDownStreamPmConfiguration and related Libraries
To fix incorrect PCIE ASPM and L1 Configuration
Implementation is silicon-dependent due to registers definition
This implementation is using the following ADL PCIE PM PATCH as reference
3bbfe44bec
Signed-off-by: kokweich <kok.wei.chan@intel.com>
Cause by cefbf78dae.
The default build will include the DACM region and the replace file should be present during stitch step.
Add fusa stitch option for users who want to replace that component in the BIOS.
Signed-off-by: Randy <randy.lin@intel.com>
- FSP version is NEX RPL-P MR2 (0C.01.DE.40)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.2
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Use MeChipsetLib from the Common Soc package and remove
Silicon specific as its redundant
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This commit has the following changes:
1. Incorporates the omitted PcdAdlLpSupport to ensure the proper GPIO groups
are loaded for ADL-N.
2. Corrects the ACPI definitions for ADL-N GPIO communities.
3. Aligns the _HID of the ADL-N GPIO Controller with the Linux kernel's
pinctrl driver.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Ethernet auto-negotiation failed since the ACPI calling method of
Windows GbE driver is changed from "_IPC" to "IPCG",
starting from version 5.123.23.601. Hence, in INTC1033 ACPI device,
change the ACPI method name accordingly.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Removed commented code and debug port80 output.
UART debug port is hard-coded to 2. this should come
from the board configuration.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* Update FSP/UCODE/for MR5 release
- update FSP version to IoT ADL-N MR5 (0C028940)
- update Microcode version to 17
- update platform version to 1.5
Basic boot tested on ADL-N CRB.
Signed-off-by: Randy <randy.lin@intel.com>
Add support for Up Xtreme i12 RPL-P based board.
The PCIe M.2 slot CN11 on the board is able to detect NVMe SSD.
Debug output is enabled at header CN9 on the board(e.g. UART1)
Tested to boot with OS loader payload and UEFI payload.
To stitch the SlimBootloader.bin with IFWI uses StitchLoader.py script with '-p' as given below:
python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/rplp/SlimBootloader.bin -o sbl_upx12rp_ifwi.bin -p 0xAA000114
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
When the fsp.git commit id is updated,
it will update all platform fsp versions without testing.
Also adjust the fd size in adln50 project to avoid build break.
Signed-off-by: Randy <randy.lin@intel.com>
The patch improves the dev experience for configuring FSP-M UPDs:
RsvdSmbusAddressTablePtr and PchNumRsvdSmbusAddresses: Prior to this patch,
developers had to apply a memory patch at address 0xfffc3ff8, which was
cumbersome and inconvenient. With the introduction of this patch, developers
can now directly modify the DLT, simplifying the configuration steps and
improving workflow efficiency.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Vincent Chen