Commit Graph

6621 Commits

Author SHA1 Message Date
Yang,Yu-chu a141bfdf55 config-tools: refine log area start address allocation
Allocates the log area start address using the same size as native environment.

Tracked-On: #6320
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-23 14:55:11 +08:00
Kunhui-Li b420b3b52f config_tools: remove the log of sucessfully generating board XML
remove the log "<board>.xml has been generated successfully!" in
board_parser.py, because it only mean that the board xml file have
been created sucessfully here, not the all data have been appended
successfully and pretty formatted.

Tracked-On: #6315
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-23 14:50:23 +08:00
David B. Kinder bbe76d6b2a doc: GSG tweaks for DX
- mention usefulness of a fast computer for improving build time
- move Ubuntu boot USB drive earlier in the list of prereqs
- move some sentences around for clarity
- improve appearance with some more spacing after images

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2021-08-22 21:43:21 -07:00
David B. Kinder 50094fb88b doc: DX update for GSG
- Update the Getting Started material with a DX-inspired rewrite and
  simplification.
- Remove duplicate and out-of-date "Building from Source"
  document, deferring to the new GSG.
- Add a development overview document.
- Move other GSGs to the advanced guides section.
- Update links in other documents to aim at the new GSG.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Amy Reyes <amy.reyes@intel.com>
2021-08-20 07:53:18 -07:00
Kunhui-Li adcf51e5f5 config_tools: fix UI issue of creating new settings
1. as a workaround, comment the code to check MBA_DELAY tag when
creating a new scenario xml setting because of this tag are retrived
from scenario xml files in generic_board folder where it is removed
now.
2. update the template launch xml file names according the recent
update for launch xml files in generic folder.

Tracked-On: #6315
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-20 11:08:19 +08:00
Liang Yi 499f62e8bd hv: use per platform maximum physical address width
MAXIMUM_PA_WIDTH will be calculated from board information.

Tracked-On: #6357
Signed-off-by: Liang Yi <yi.liang@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-20 11:02:21 +08:00
Liang Yi 2b3620de7d hv: mask off LA57 in cpuid
Mask off support of 57-bit linear addresses and five-level paging.

ICX-D has LA57 but ACRN doesn't support 5-level paging yet.

Tracked-On: #6357
Signed-off-by: Liang Yi <yi.liang@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2021-08-20 11:02:21 +08:00
Shiqing Gao 91777a83b5 config_tools: add a new entry MAX_EFI_MMAP_ENTRIES
It is used to specify the maximum number of EFI memmap entries.

On some platforms, like Tiger Lake, the number of EFI memmap entries
becomes 268 when the BIOS settings are changed.
The current value of MAX_EFI_MMAP_ENTRIES (256) defined in hypervisor
is not big enough to cover such cases.

As the number of EFI memmap entries depends on the platforms and the
BIOS settings, this patch introduces a new entry MAX_EFI_MMAP_ENTRIES
in configurations so that it can be adjusted for different cases.

Tracked-On: #6442

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2021-08-20 09:50:39 +08:00
Shiqing Gao 651d44432c hv: initialize the XSAVE related processor state for guest
If SOS is using kernel 5.4, hypervisor got panic with #GP.

Here is an example on KBL showing how the panic occurs when kernel 5.4 is used:
Notes:
 * Physical MSR_IA32_XSS[bit 8] is 1 when physical CPU boots up.
 * vcpu_get_guest_msr(vcpu, MSR_IA32_XSS)[bit 8] is initialized to 0.

Following thread switches would happen at run time:
1. idle thread -> vcpu thread
   context_switch_in happens and rstore_xsave_area is called.
   At this moment, vcpu->arch.xsave_enabled is false as vcpu is not launched yet
   and init_vmcs is not called yet (where xsave_enabled is set to true).
   Thus, physical MSR_IA32_XSS is not updated with the value of guest MSR_IA32_XSS.

   States at this point:
    * Physical MSR_IA32_XSS[bit 8] is 1.
    * vcpu_get_guest_msr(vcpu, MSR_IA32_XSS)[bit 8] is 0.

2. vcpu thread -> idle thread
   context_switch_out happens and save_xsave_area is called.
   At this moment, vcpu->arch.xsave_enabled is true. Processor state is saved
   to memory with XSAVES instruction. As physical MSR_IA32_XSS[bit 8] is 1,
   ectx->xs_area.xsave_hdr.hdr.xcomp_bv[bit 8] is set to 1 after the execution
   of XSAVES instruction.

   States at this point:
    * Physical MSR_IA32_XSS[bit 8] is 1.
    * vcpu_get_guest_msr(vcpu, MSR_IA32_XSS)[bit 8] is 0.
    * ectx->xs_area.xsave_hdr.hdr.xcomp_bv[bit 8] is 1.

3. idle thread -> vcpu thread
   context_switch_in happens and rstore_xsave_area is called.
   At this moment, vcpu->arch.xsave_enabled is true. Physical MSR_IA32_XSS is
   updated with the value of guest MSR_IA32_XSS, which is 0.

   States at this point:
    * Physical MSR_IA32_XSS[bit 8] is 0.
    * vcpu_get_guest_msr(vcpu, MSR_IA32_XSS)[bit 8] is 0.
    * ectx->xs_area.xsave_hdr.hdr.xcomp_bv[bit 8] is 1.

   Processor state is restored from memory with XRSTORS instruction afterwards.
   According to SDM Vol1 13.12 OPERATION OF XRSTORS, a #GP occurs if XCOMP_BV
   sets a bit in the range 62:0 that is not set in XCR0 | IA32_XSS.
   So, #GP occurs once XRSTORS instruction is executed.

Such issue does not happen with kernel 5.10. Because kernel 5.10 writes to
MSR_IA32_XSS during initialization, while kernel 5.4 does not do such write.
Once guest writes to MSR_IA32_XSS, it would be trapped to hypervisor, then,
physical MSR_IA32_XSS and the value of MSR_IA32_XSS in vcpu->arch.guest_msrs
are updated with the value specified by guest. So, in the point 2 above,
correct processor state is saved. And #GP would not happen in the point 3.

This patch initializes the XSAVE related processor state for guest.
If vcpu is not launched yet, the processor state is initialized according to
the initial value of vcpu_get_guest_msr(vcpu, MSR_IA32_XSS), ectx->xcr0,
and ectx->xs_area. With this approach, the physical processor state is
consistent with the one presented to guest.

Tracked-On: #6434

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Li Fei1 <fei1.li@intel.com>
2021-08-20 09:46:09 +08:00
Zide Chen 2e6cf2b85b hv: nested: fix bugs in init_vmx_msrs()
Currently init_vmx_msrs() emulates same value for the IA32_VMX_xxx_CTLS
and IA32_VMX_TRUE_xxx_CTLS MSRs.

But the value of physical MSRs could be different between the pair,
and we need to adjust the emulated value accordingly.

Tracked-On: #6289
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-20 09:40:50 +08:00
Zide Chen ad37553873 hv: nested: redundant permission check on nested_vmentry()
check_vmx_permission() is called in vmresume_vmexit_handler() and
vmlaunch_vmexit_handler() already.

Tracked-On: #6289
Signed-off-by: Zide Chen <zide.chen@intel.com>
2021-08-20 08:14:40 +08:00
Yifan Liu d575edf79a hv: Change sched_event structure to resolve data race in event handling
Currently the sched event handling may encounter data race problem, and
as a result some vcpus might be stalled forever.

One example can be wbinvd handling where more than 1 vcpus are doing
wbinvd concurrently. The following is a possible execution of 3 vcpus:
-------
0                            1                           2
                             req [Note: 0]
                             req bit0 set [Note: 1]
                             IPI -> 0
                             req bit2 set
                             IPI -> 2
                                                         VMExit
                                                         req bit2 cleared
                                                         wait
                                                         vcpu2 descheduled

VMExit
req bit0 cleared
wait
vcpu0 descheduled
                             signal 0
                             event0->set=true
                             wake 0

                             signal 2
                             event2->set=true [Note: 3]
                             wake 2
                                                         vcpu2 scheduled
                                                         event2->set=false
                                                         resume

                                                         req
                                                         req bit0 set
                                                         IPI -> 0
                                                         req bit1 set
                                                         IPI -> 1
                             (doesn't matter)
vcpu0 scheduled [Note: 4]
                                                         signal 0
                                                         event0->set=true
                                                         (no wake) [Note: 2]
event0->set=false                                        (the rest doesn't matter)
resume

Any VMExit
req bit0 cleared
wait
idle running

(blocked forever)

Notes:
0: req: vcpu_make_request(vcpu, ACRN_REQUEST_WAIT_WBINVD).
1: req bit: Bit in pending_req_bits. Bit0 stands for bit for vcpu0.
2: In function signal_event, At this time the event->waiting_thread
    is not NULL, so wake_thread will not execute
3: eventX: struct sched_event of vcpuX.
4: In function wait_event, the lock does not strictly cover the execution between
    schedule() and event->set=false, so other threads may kick in.
-----

As shown in above example, before the last random VMExit, vcpu0 ended up
with request bit set but event->set==false, so blocked forever.

This patch proposes to change event->set from a boolean variable to an
integer. The semantic is very similar to a semaphore. The wait_event
will add 1 to this value, and block when this value is > 0, whereas signal_event
will decrease this value by 1.

It may happen that this value was decreased to a negative number but that
is OK. As long as the wait_event and signal_event are paired and
program order is observed (that is, wait_event always happens-before signal_event
on a single vcpu), this value will eventually be 0.

Tracked-On: #6405
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
2021-08-20 08:11:40 +08:00
Kunhui-Li bbc92361bc config_tools: update lpc slot number in script
Update lpc slot to origin value 1 from 31 in the script too,
because GOP driver has assumption to config space layout of
the device on 00:1f.0.

Tracked-On: #6340
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-20 08:07:43 +08:00
Kunhui-Li a860af24ba config_tools: rename python script
1. rename “cli.py” to “board_inspector.py”,
   and update the script name in README file.
2. rename “app.py” to “acrn_configurator.py”.

Tracked-On: #6417
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-20 07:58:23 +08:00
Liu Long 4d8623ffc0 ACRN:DM: Fix the Null pointer error
Function virtio_console_close_all will close all consoles, if the console->nports
value is 1, after the console be destroyed by the mevent teardown function, when
get the nports from the console, there will cause the NULL pointer. Fix the issue.

Tracked-On: #6431
Signed-off-by: Liu Long long.liu@intel.com
Reviewed-by: Jian Jun Chen jian.jun.chen@intel.com
Acked-by: Wang, Yu1 yu1.wang@intel.com
2021-08-20 07:55:25 +08:00
Kunhui-Li a73dd7b5f7 config_tools: disable TPM2 passthrough on other platforms
Disables TPM2 passthrough on other platforms except TGL
follow the 6410 PR.

Tracked-On: #6288
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-20 07:53:30 +08:00
David B. Kinder 331c66bde8 doc: update configuration tool names
PR #6418 renames the board inspector tool cli.py to board_inspector.py
and the configuration tool app.py to acrn_configurator.py

Update the documentation to use these new names.  Note that the ROScube
GSG is validated with ACRN v2.1 and instructs the user to checkout that
branch where the tool is still called app.py

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2021-08-19 16:34:08 -07:00
Kunhui-Li f0a38692cf config_tools: fix the issue that fail to generate launch script
fix the issue that fail to generate launch script when to disable
CPU sharing.

Tracked-On: #6428
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-19 20:09:58 +08:00
Zhou, Wu 2e2730137f HV: Change hybrid.xml default zephyr config to KERNEL_ELF
In the default config file for hybrid scenario, zephyr image was
configured as KERNEL_RAWIMAGE. Now we change them to KERNEL_ELF
for all the platforms. And also kernel mods are changed from
Zephyr_RawImage to Zephyr_ElfImage

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu b394777908 HV: Add implements of 32bit and 64bit elf loader
This is a simply implement for the 32bit and 64bit elf loader.

The loading function first reads the image header, and finds the program
entries that are marked as PT_LOAD, then loads segments from elf file to
guest ram. After that, it finds the bss section in the elf section entries, and
clear the ram area it points to.

Limitations:
1. The e_type of the elf image must be ET_EXEC(executable). Relocatable or
   dynamic code is not supported.
2. The loader only copies program segments that has a p_type of
   PT_LOAD(loadable segment). Other segments are ignored.
3. The loader doesn’t support Sections that are relocatable
   (sh_type is SHT_REL or SHT_RELA)
4. The 64bit elf’s entry address must below 4G.
5. The elf is assumed to be able to put segments to valid guest memory.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu c2468d2791 HV: Add elf loader sketch
This patch adds a function elf_loader() to load elf image.
It checks the elf header, get its 32/64 bit type, then calls
the corresponding loading routines, which are empty, and
will be realized later.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu 537f69dde9 HV: Add elf header file for elf loader
Source: https://github.com/freebsd/freebsd-src/blob/main/sys/sys/elf_common.h
Trimed to meet the minimal requirements for the Zephyr elf file to be loaded
Also added elf file header data struct and program/section entry data structs.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu 8100b1dd56 HV: Remove 'vm_' of vm_elf_loader and etc.
In order to make better sense, vm_elf_loader, vm_bzimage_loader and
vm_rawimage_loader are changed to elf_loaer, bzimage_loaer and
rawimage_loader.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu 53f6720d13 HV: Combine the acpi loading fucntion to one place
Remove the acpi loading function from elf_loader, rawimage_loaer and
bzimage_loader, and call it together in vm_sw_loader.

Now the vm_sw_loader's job is not just loading sw, so we rename it to
prepare_os_image.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Zhou, Wu e78aacbe55 HV: Correct some naming issues
For the guest OS loaders, prapare_loading_xxx are not accurate for
what those functions actually do. Now they are changed to load_xxx:
load_rawimage, load_bzimage.

And the 'bsp' expression is confusing in the comments for
init_vcpu_protect_mode_regs, changed to a better way.

Tracked-On: #6323

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Victor Sun 3124018917 HV: vm_load: rename vboot_info.h to vboot.h
vboot_info.h declares vm loader function also, so rename the file name to
vboot.h;

Tracked-On: #6323

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Victor Sun 9b632c0e4b HV: vm_load: split vm_load.c to support diff kernel format
The patch splits the vm_load.c to three parts, the loader function of bzImage
kernel is moved to bzimage_loader.c, the loader function of raw image kernel
is moved to rawimage_loader.c, the stub is still stayed in vm_load.c to load
the corresponding kernel loader function. Each loader function could be
isolated by CONFIG_GUEST_KERNEL_XXX macro which generated by config tool.

Tracked-On: #6323

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Victor Sun 2524572fb2 HV: vm_load: refine vm_sw_loader API
Change if condition to switch in vm_sw_loader() so that the sw loader
could be compiled conditionally.

Tracked-On: #6323

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Yang,Yu-chu 73dc610d90 config-tool: refine guest kernel types
Rename KERNEL_ZEPHYR to KERNEL_RAWIMAGE. Added new type "KERNEL_ELF".

Add CONFIG_GUEST_KERNEL_RAWIMAGE, CONFIG_GUEST_KERNEL_ELF and/or
CONFIG_GUEST_KERNEL_BZIMAGE to config.h if it's configured.

Tracked-On: #6323

Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
2021-08-19 20:00:45 +08:00
Victor Sun 178b3e85e3 HV: vm_load: change kernel type for zephyr image
Previously we only support loading raw format of zephyr image as prelaunched
Zephyr VM, this would cause guest F segment overridden issue because the zephyr
raw image covers memory space from 0x1000 to 0x100000 upper. To fix this issue,
we should support ELF format image loading so that parse and load the multiple
segments from ELF image directly.

Tracked-On: #6323

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-19 20:00:45 +08:00
Kunhui-Li cf1f3ac51d config_tools: remove some tags check for scenario.xml in generic_board folder
remove some tags check for scenario xml files in generic_board folder when
importing a new type of board in UI, and minor fix for the warning of config
editor.

Tracked-On: #6315
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-19 15:41:34 +08:00
Liu,Junming a83d880f11 dm: update the GPU OpRegion size to 20KB
The address of OpRegion is not 4KB aligned,
if the OpRegion + extended VBT size is 16KB,
then it will take up to 5 physical pages in host.
So update the OpRegion size to 20KB
to expose the whole OpRegion to guest.

Tracked-On: #6270

Signed-off-by: Liu,Junming <junming.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2021-08-19 13:09:21 +08:00
Fei Li 2e7491a8ec hv: mmiodev: a minor bug fix about refine acrn_mmiodev data structure
Rename base_hpa to host_pa in acrn_mmiodev data structure.

Tracked-On: #6366
Signed-off-by: Fei Li <fei1.li@intel.com>
2021-08-19 12:01:35 +08:00
Liu,Junming 2c5c8754de hv:enable GVT-d for pre-launched linux guest in logical partion mode
When pass-thru GPU to pre-launched Linux guest,
need to pass GPU OpRegion to the guest.
Here's the detailed steps:
1. reserve a memory region in ve820 table for GPU OpRegion
2. build EPT mapping for GPU OpRegion to pass-thru OpRegion to guest
3. emulate the pci config register for OpRegion
For the third step, here's detailed description:
The address of OpRegion locates on PCI config space offset 0xFC,
Normal Linux guest won't write this register,
so we can regard this register as read-only.
When guest reads this register, return the emulated value.
When guest writes this register, ignore the operation.

Tracked-On: #6387

Signed-off-by: Liu,Junming <junming.liu@intel.com>
2021-08-19 11:56:26 +08:00
Junjie Mao 1dca1da96d config_tools: rename two missed PSRAMs to SSRAMs
The term PSRAM is now obsoleted and should be replaced with SSRAM, as has been
done by commit 9facbb43b3 ("config-tool: rename PSRAM to SSRAM"). However,
there are two places in the configuration toolset that still uses PSRAM. This
patch updates these missed occurrences accordingly.

Tracked-On: #6012
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-19 10:48:15 +08:00
Liu, Hang1 3964167774 doc:resolve the mismatch between doc and code
Default e820 mem map in hld-devicemodel.rst is
mismatched with sw_load_common.c,update the doc
to align with code.

Signed-off-by: Liu, Hang1 <hang1.liu@intel.com>
2021-08-18 09:15:38 -07:00
Junjie Mao cd31310f65 FIXME: temporarily disable TPM2 passthrough
On some boards it is seen that the log area of the physical TPM2 is
programmed to be 0. If TPM2 is passed through to a pre-launched VM in such
cases, a piece of memory starting from GPA 0 will be unmapped from the
Service VM, leading to Service VM crash due to early BIOS corruption
checks.

This patch temporarily disables TPM2 passthrough on such platforms. A
thorough fix should be proposed later to gracefully handle such cases.

Tracked-On: #6288
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-18 13:08:29 +08:00
Yang,Yu-chu 668ae81048 config-tools: replace xml.etree.ElementTree with defusedxml.ElementTree
Using xml.etree.ElementTree to parse the untrusted data is known to
raise security issue. Replaced it using defusedxml.

Tracked-On: #6342
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-13 16:11:42 +08:00
Yang,Yu-chu c10ac227cc config-tools: remove unused package and add nosec to subprocess
The subprocess module is needed for calling package from python script.
Add #nosec for subprocess module importing.

Tracked-On: #6342
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-13 16:11:42 +08:00
Jian Jun Chen dc77ef9e52 hv: ivshmem: map SHM BAR with PAT ignored
ACRN does not support the variable range vMTRR. The default
memory type of vMTRR is UC. With this vMTRR emulation guest VM
such as Linux refuses to map the MMIO address space as WB. In
order to get better performance SHM BAR of ivshmem is mapped
with PAT ignored and memory type of SHM BAR is fixed to WB.

Tracked-On: #6389
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2021-08-13 11:17:15 +08:00
Kunhui-Li 1d952cfba1 config_tools: update the board xml files
update the board xml and related scenario xml files because the
PR 6352 update the board inspector code to get more board info.

Tracked-On: #6298
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-08-13 11:14:54 +08:00
Yang,Yu-chu a4be0aa57b config-tools: add native log area address
Extract the log area address from TPM2 acpi table and add node
log_area_start_address to board.xml. This emelment is used by host_pa of
mmiodevs.

Tracked-On: #6320
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-13 11:09:01 +08:00
Yonghua Huang d92c4bd840 dm: fix potential NULL pointer access in virtio_console.c
"port->cb" in 'virtio_console_notify_tx()'
 function maybe NULL when malicious inputs
 are injected from virtio frondend in guest.

Tracked-On: #6388
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2021-08-13 10:52:29 +08:00
Liu, Hang1 1f5a7e8b8d doc:add more explanation on parameter --windows
acrn-dm --windows parameter is used for specify
the Windows ORACLE virtio device driver,which is
used when enable secure boot in Windows, otherwise
the default REDHAT virtio device driver will be
used which is not certified by Microsoft

Signed-off-by: Liu, Hang1 <hang1.liu@intel.com>
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2021-08-12 09:39:00 -07:00
Junjie Mao 4c04857681 config_tools: fix formatting of configured INTx allocation
There could be multiple ways in the scenario configuration to specify that
no INTx allocation is explicitly allocation to a prelaunched VM:

  * Do not have a `pt_intx` node at all.

  * Have a `pt_intx` node with no text.

  * Have a `pt_intx` node with a text that has nothing but whitespaces,
    tabs and newlines.

The current implementation only supports the first way, and will cause
build-time failures when a scenario configuration uses the latter two. The
following changes are introduced by this patch to fix such errors.

  * The INTx static allocator queries the text() of `pt_intx` nodes
    directly to gracefully handle `pt_intx` nodes with no text.

  * The XSLT of pt_intx.c clears all kinds of white spaces from the text of
    `pt_intx` nodes before calculating the set of allocated INTx mappings.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-12 08:56:56 +08:00
David B. Kinder 2216134cf4 doc: update config data descriptions
Fix some formatting issues in PR #6378

Tracked-On: #6377

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2021-08-11 13:56:04 -07:00
Shiqing Gao de19301a5a config_tools: refine the configuration data description
This patch refines the configuration data description so that it is
consistent with the current implementation of the configuration tools.

Tracked-On: #6377

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2021-08-11 16:38:35 +08:00
Fei Li 3df703a64e config-tools: add SECURITY_VM_FIXUP config
Add SECURITY_VM_FIXUP config for Security VM whether it needs to do fixup
for TPM2 and SMBIOS

Tracked-On: #6320
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Fei Li <fei1.li@intel.com>
2021-08-11 14:45:55 +08:00
Yang,Yu-chu d997f4bbc1 config-tools: refine bin_gen.py and create virtual TPM2 acpi table
Create virtual acpi table of tpm2 based on the raw data if the TPM2
device is presented and the passthrough tpm2 is enabled.

Refine the arguments of bin_gen.py. The --board and --scenario take the
path to the XMLs as the argument. The allocation.xml is needed for
bin_gen.py to generate tpm2 acpi table.

Refine the condition of tpm2_acpi_gen. The tpm2 device "MSFT0101" can be
present in device id or compatible_id(CID). Check both attributes and
child node of tpm2 device.

Tracked-On: #6320
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-11 14:45:55 +08:00
Yang,Yu-chu 53d99d2a68 config-tools: generate the log area data of tpm2
Insert the passthrough tpm2 datas to mmiodevs of vm_configurations.c

Tracked-On: #6320
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-08-11 14:45:55 +08:00