config_tools: add a new entry MAX_EFI_MMAP_ENTRIES
It is used to specify the maximum number of EFI memmap entries. On some platforms, like Tiger Lake, the number of EFI memmap entries becomes 268 when the BIOS settings are changed. The current value of MAX_EFI_MMAP_ENTRIES (256) defined in hypervisor is not big enough to cover such cases. As the number of EFI memmap entries depends on the platforms and the BIOS settings, this patch introduces a new entry MAX_EFI_MMAP_ENTRIES in configurations so that it can be adjusted for different cases. Tracked-On: #6442 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This commit is contained in:
parent
651d44432c
commit
91777a83b5
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@ -11,7 +11,7 @@
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#include <logmsg.h>
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static uint16_t hv_memdesc_nr;
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static struct efi_memory_desc hv_memdesc[MAX_EFI_MMAP_ENTRIES];
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static struct efi_memory_desc hv_memdesc[CONFIG_MAX_EFI_MMAP_ENTRIES];
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static void sort_efi_mmap_entries(void)
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{
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@ -37,8 +37,8 @@ void init_efi_mmap_entries(struct efi_info *uefi_info)
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uint32_t entry = 0U;
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while ((void *)efi_memdesc < (efi_memmap + uefi_info->memmap_size)) {
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if (entry >= MAX_EFI_MMAP_ENTRIES) {
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pr_err("Too many efi memmap entries, entries up %d are ignored.", MAX_EFI_MMAP_ENTRIES);
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if (entry >= CONFIG_MAX_EFI_MMAP_ENTRIES) {
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pr_err("Too many efi memmap entries, entries up %d are ignored.", CONFIG_MAX_EFI_MMAP_ENTRIES);
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break;
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}
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@ -8,8 +8,6 @@
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#define EFI_MMAP_H
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#include <types.h>
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#define MAX_EFI_MMAP_ENTRIES 256U
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void init_efi_mmap_entries(struct efi_info *uefi_info);
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uint32_t get_efi_mmap_entries_count(void);
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@ -44,6 +44,7 @@
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -44,6 +44,7 @@
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -57,6 +57,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -57,6 +57,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -60,6 +60,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -57,6 +57,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -60,6 +60,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -57,6 +57,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -48,6 +48,7 @@
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>300</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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@ -55,6 +55,7 @@
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>300</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</MEMORY>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>300</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>300</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>300</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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<CAPACITIES>
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<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
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<MAX_EFI_MMAP_ENTRIES>256</MAX_EFI_MMAP_ENTRIES>
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<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
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<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
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<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
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</xs:restriction>
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</xs:simpleType>
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</xs:element>
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<xs:element name="MAX_EFI_MMAP_ENTRIES" type="xs:integer" default="256">
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<xs:annotation>
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<xs:documentation>The maximum number of EFI memmap entries.</xs:documentation>
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</xs:annotation>
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</xs:element>
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<xs:element name="MAX_PT_IRQ_ENTRIES" type="xs:integer" default="256">
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<xs:annotation>
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<xs:documentation>The pre-defined number of interrupt sources of all pass-through devices.</xs:documentation>
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@ -167,6 +167,10 @@
|
|||
<xsl:with-param name="key" select="'MAX_IOAPIC_NUM'" />
|
||||
</xsl:call-template>
|
||||
|
||||
<xsl:call-template name="integer-by-key">
|
||||
<xsl:with-param name="key" select="'MAX_EFI_MMAP_ENTRIES'" />
|
||||
</xsl:call-template>
|
||||
|
||||
<xsl:call-template name="integer-by-key">
|
||||
<xsl:with-param name="key" select="'MAX_IR_ENTRIES'" />
|
||||
</xsl:call-template>
|
||||
|
|
Loading…
Reference in New Issue