Commit Graph

3766 Commits

Author SHA1 Message Date
dongshen 0247c0b942 Hv: minor cosmetic fix
Define/Use variable in place of code to improve readability:

Define new local variable struct pci_bar *vbar, and use vbar-> in place of vdev->bar[idx].

Define new local variable uint64_t vbar_base in init_vdev_pt

Rename uint64_t vbar[PCI_BAR_COUNT] of struct acrn_vm_pci_ptdev_config to uint64_t vbar_base[PCI_BAR_COUNT]

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen f0244b24e7 HV: call get_vbar_base() to get the newly set vbar base address in 64-bit
Replace new_base with vbar_base in vdev_pt_remap_generic_mem_vbar().
We will call vdev_pt_remap_generic_mem_vbar() after a new vbar base
is set, no need to pass new_base to vdev_pt_remap_generic_mem_vbar(),
as this new vbar base (vbar_base) can be obtained by calling get_vbar_base().

The reason we call vdev_pt_remap_generic_mem_vbar() after a new vbar base
is set is for 64-bit mmio handling: when the lower 32-bit of 64-bit mmio vbar is
set, we will defer calling vdev_pt_remap_generic_mem_vbar until its upper 32-bit
vbar base is set.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen ed1bdcbbdf HV: add uint64_t bar_base_mapped[PCI_BAR_COUNT] to struct pci_vdev
To remember the previously mapped/registered vbar base

For the following reasons:
 register_mmio_emulation_handler() will throw an error if the the same addr_lo is
 alreayd registered before

 We are going to remove the base member from struct pci_bar, so we cannot use vdev->bar[idx].base
 in the code any more

 In subsequent commits, we will assume vdev_pt_remap_generic_mem_vbar() is called after a new
 vbar base is set, mainly because of 64-bit mmio bar handling, so we need a
 separate bar_base_mapped[] array to track the previously mapped vbar bases.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen 65ca6ae498 HV: add get_vbar_base() to get vbar base address in 64-bit
vbar base can be built by using the base address fields stored in
struct pci_bar's reg member.

get_vbar_base: return vbar's base address in 64-bit. For 64-bit MMIO bar, its lower 32-bits
base address and upper 32-bits base are combined into one 64-bit base address

And changed related code to use get_vbar_base to get vbar base address in
64-bit.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen 7a2f52441b HV: store the vbar base address in vbar's reg member
We added "union pci_bar_reg reg" to struct pci_bar in previous commit,
but only pci_pdev uses it and pci_vdev does not use it. Starting from
this commit, pci_vdev will use it:

In init_vdev_pt(), copy pbar's reg's flags portion to corresponding vbar's
reg.

When guest updates the vbar base address, the corresponding vbar reg's base
address will also be updated, so that in subsequent commits, we can eventually
remove the base member in struct pci_bar.

Rename local variable new_bar to base in vdev_pt_write_vbar

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen 1b4dbdab70 HV: add get_pbar_base() to get pbar base address in 64-bit
pbar base can be built by using the base address fields stored in
struct pci_bar's reg member.

get_pbar_base: return pbar's base address in 64-bit. For 64-bit MMIO bar, its lower 32-bits
base address and upper 32-bits base are combined into one 64-bit base address

pci_bar_2_bar_base: helper function that is called by get_pbar_base

And changed related code to use get_pbar_base to get pbar base address in 64-bit

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
dongshen 8707834f83 HV: remove the function get_bar_base()
There is no need to call get_bar_base(), as new_bar is set to val & mask,
where mask is the bar size mask, so new_base has already been set to be the
bar base address before get_bar_base() is called on it.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-07-01 09:57:05 +08:00
Huihuang Shi 74b788988d HV:fix vcpu more than one return entry
ACRN coding guideline requires function shall have only one return entry.
Fix it.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-28 13:28:26 +08:00
Huihuang Shi 198e01716a HV:fix vcpu violations
vcpu is never scan because of scan tool will be crashed!
After modulization, the vcpu can be scaned by the scan tool.
Clean up the violations in vcpu.c.
Fix the violations:
    1.No brackets to then/else.
    2.Function return value not checked.
    3.Signed/unsigned coversion without cast.

V1->V2:
    change the type of "vcpu->arch.irq_window_enabled" to bool.
V2->V3:
    add "void *" prefix on the 1st parameter of memset.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-28 13:28:26 +08:00
Jack Ren dc510030d2 version: 1.2-unstable
Signed-off-by: Jack Ren <jack.ren@intel.com>
2019-06-28 11:09:28 +08:00
Yan, Like c42b41fe2b dm: add "noapic" to rt-linux kernel parameters
This commit adds "noapic" boot option to rt-linux, to skip IOAPIC probe.

Tracked-On: #3227
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-06-28 09:36:41 +08:00
David B. Kinder 2376b3af5c doc: update doc version menu
Update the /latest/ (master) version of the docs to provide the menu
choice for the v1.1 release.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-06-27 14:56:41 -07:00
ruix.li 680edd1d3c doc: Update acrn-manager README and QoS introduction
Modify 'launch_UOS.sh' to 'launch_uos.sh' and provide an example for
the script which is support '-C' option.

Signed-off-by: ruix.li <ruix.li@intel.com>
2019-06-27 14:41:06 -07:00
ruix.li 5bee933885 doc: Add v1.1 release note
v1.1 release note

Signed-off-by: ruix.li <ruix.li@intel.com>
2019-06-27 14:13:29 -07:00
Geoffroy Van Cutsem 9b2b4cd84c tools: enhance online and built-in help messages
Enhance and re-order the help messages for the `acrnd` tools (daemon for
ACRN VM management). Fix a few typos in the process.

Tracked-On: #3329
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2019-06-27 21:19:28 +08:00
Conghui Chen 8badd0b486 DM: virtio-console: bug fix for parsing options
Bug fix for parsing options, as the vritio-console support multiple
virtio serial ports, and the parameters is split by ',':

virtio-console,[@]stdio|tty|pty|file:portname[=portpath]\
   [,[@]stdio|tty|pty|file:portname[=portpath]]

But the previous patch "refine console options parse code" not
cover this case, can only parse one port config. Fix it in this patch.

Tracked-On: #3337
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
2019-06-27 16:42:09 +08:00
Conghui Chen 4d88b2bb65 hv: bugfix for sbuf reset
The sbuf is allocated for each pcpu by hypercall from SOS. Before launch
Guest OS, the script will offline cpus, which will trigger vcpu reset and
then reset sbuf pointer. But sbuf only initiate once by SOS, so these
cpus for Guest OS has no sbuf to use. Thus, when run 'acrntrace' on SOS,
there is no trace data for Guest OS.
To fix the issue, only reset the sbuf for SOS.

Tracked-On: #3335
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
2019-06-27 15:40:19 +08:00
dongshen f7c4d2b5c4 HV: add uint32_t nr_bars to struct pci_vdev
Use nr_bars instead of PCI_BAR_COUNT to check bar access offset.
As while normal pci device has max 6 bars, pci bridge only has 2 bars,
so for pci normal pci device, pci cfg offsets 0x10-0x24 are for bar access,
but for pci bridge, only 0x10-0x14 are for bar access (0x18-0x24 are
for other accesses).

Rename function:
 pci_bar_access --> is_bar_offset

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
dongshen 28d454bfb9 HV: move bar access and alignment checking out of vdev_pt_write_vbar
And put the checking in vdev_pt_write_cfg instead to have less nesting in
vdev_pt_write_vbar to improve code readability.

Rename function:
vdev_pt_remap_generic_bar --> vdev_pt_remap_generic_mem_vbar

vdev_pt_read_cfg's function declaration is merged into one line instead of 2
lines

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
dongshen 208b1d3664 HV: add uint32_t nr_bars to struct struct pci_pdev to track # of bars
nr_bars in struct pci_pdev is used to store the actual # of bars (
6 for normal pci device and 2 for pci bridge), nr_bars will be used in subsequent
patches

Use uint32_t for bar related variables (bar index, etc) to unify the bar
related code (no casting between uint32_t and uint8_t)

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
dongshen 95d10d8921 HV: add union pci_bar and is_64bit_high to struct pci_bar
union pci_bar uses bit fields and follows the PCI bar spec definition to define the
bar flags portion and base address, this is to keep the same hardware format for vbar
register. The base/type of union pci_bar are still kept to minimize code changes
in one patch, they will be removed in subsequent patches.

define pci_pdev_get_bar_base() function to extract bar base address given a 32-bit raw
bar value

define a utility function pci_get_bar_type() to extract bar types
from raw bar value to simply code, as this function will be used in multiple
places later on: this function can be called on reg->value stored in struct
pci_bar to derive bar type.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
dongshen 3e3be6ba50 HV: for PCI cardbus device, its capability offset is at offset 0x14
Add get_offset_of_caplist() function to return capability offset based on header type:
For normal pci device and bridge, its capability offset is at offset 0x34
For cardbus, its capability offset is at offset 0x14

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
dongshen c61ea3b5af HV: remove unused function find_pci_pdev
find_pci_pdev is not used any more, remove it.

Tracked-On: #3241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-27 15:35:16 +08:00
Binbin Wu ad6f54b99a dm: sample: remove deprecated sos_bootargs files
SOS bootargs is specified in vm_configurations.h in different scenarios.
The files in devicemodel/samples/<board>/sos_bootargs_*.txt are not used anymore.
Remove these deprecated files to avoid confusion.

Tracked-On: #3214
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
2019-06-27 15:29:21 +08:00
Li, Fei1 e793b5d091 hv: vlapic: remove ISR vector stack
The current implement will cache each ISR vector in ISR vector stack and do
ISR vector stack check when updating PPR. However, there is no need to do this
because:
1) We will not touch vlapic->isrvec_stk[0] except doing vlapic_reset:
  So we don't need to do vlapic->isrvec_stk[0] check.
2) We only deliver higher priority interrupt from IRR to ISR:
  So we don't need to check whether vlapic->isrvec_stk interrupts is always increasing.
3) There're only 15 different priority interrupt, It will not happened that more that
15 interrupts could been delivered to ISR:
  So we don't need to check whether vlapic->isrvec_stk_top will larger than
  ISRVEC_STK_SIZE which is 16.
This patch try to remove ISR vector stack and use isrv to cache the vector number for
the highest priority bit that is set in the ISR.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-06-27 15:27:37 +08:00
Xiaoguang Wu 31e23cd09c DM USB: clean up the assert usage
Remove assert in USB mediator code.

Tracked-On: #3252
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-06-26 22:50:38 +08:00
Mingqiang Chi 7e6ff2a176 hv:fix a bug for building debug/release lib
there is a build error if we only build debug/release library
because missing the build/modules folder

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>

	modified:   Makefile
	modified:   debug/Makefile
	modified:   release/Makefile
2019-06-26 15:22:57 +08:00
Long Liu 7176e813ed ACRN: dm: Modify the runC.json for NUC.
The path modify the configuration for the runC container. There have
three changes for the configuration.
1、args [ "sh" ]: this is an example parameter and when the VM is started,
the parameter will be replaced by the launch_UOS script.
2、The linux capabilities will guarantee the Acrn-dm have enough capabilities
to run in container. For more infomation about the capalility you can refer
http://man7.org/linux/man-pages/man7/capabilities.7.htm
3、Move the rootfs to the parent directory, so all the container can share
the same rootfs.

Tracked-On: projectacrn#2020
Signed-off-by: Long Liu <long.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2019-06-26 15:22:33 +08:00
Geoffroy Van Cutsem b759708cad TravisCI: remove all config and support files related to TravisCI
The project does not make use of TravisCI. Remove all the configuration and
support files (that are also mostly bit-rotten by now).

Tracked-On: #3286
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2019-06-26 09:38:49 +08:00
Huihuang Shi 3a61530d4e HV:fix simple violations
Fix the violations not touched the logical.
1.Function return value not checked.
2.Logical conjuctions need brackets.
3.No brackets to then/else.
4.Type conversion without cast.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2019-06-25 20:09:21 +08:00
Kaige Fu c82e3fd264 HV: Debug: Add version command
When debugging the HV, we may want to check the HV version information
frequently. In current HV shell command, there is no such kind of command
to check this information. We can only scroll up the HV console log to
get the information. If there are very huge amount of lines of log, it
will be very time-wasting to get the HV version information.

So, this patch adds 'version' command to get the HV version information
conveniently.

Tracked-On: #3310
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-06-24 18:52:18 +08:00
yingbinx fbf16d7327 DM: virtio_rpmb: clean up assert
clean up assert from virtio rpmb module.

Tracked-On: #3252
Signed-off-by: dengwei <wei.a.deng@intel.com>
Signed-off-by: yingbinx <yingbinx.zeng@intel.com>
Acked-by: Zhu Bing <bing.zhu@intel.com>
2019-06-24 18:51:44 +08:00
David B. Kinder 0dc8c179e6 doc: update acrnd/acrnctl option docs
Document the acrnd -t, and acrnctl add -C options, noted as missing in
PR #3137

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-06-23 21:59:46 -07:00
Kaige Fu 217145e33b Doc: Update acrn-shell.rst for new 'version' cmd
This patch updates acrn-shell.rst for new 'version' cmd.

Tracked-On: #3310
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-06-23 21:57:12 -07:00
Jian Jun Chen 56469f3edc dm: refine assert usage
Remove unnecessary assert and add error handling when required.

Tracked-On: #3252
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-06-24 11:57:05 +08:00
Sainath Grandhi 0a8bf6cee4 hv: Avoid run-time buffer overflows with IOAPIC data structures
Remove couple of run-time ASSERTs in ioapic module by checking for the
number of interrupt pins per IO-APICs against the configured MAX_IOAPIC_LINES
in the initialization flow.
Also remove the need for two MACROs specifying the max. number of
interrupt lines per IO-APIC and add a config item MAX_IOAPIC_LINES for the
same.

Tracked-On: #3299
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-24 11:41:10 +08:00
Mingqiang Chi c1e23f1a4a hv:Fix MISRA-C violations for static inline
MISRA-C requires inline functions should be declared static,
these APIs are external interfaces,remove inline

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>

	modified:   arch/x86/guest/vcpu.c
2019-06-24 08:31:32 +08:00
Gao Junhao 93b4cf57fa dm: clean up assert in virtio.c
clean up assert in virtio.c

Tracked-On: #3302
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-06-22 21:42:32 +08:00
Gao Junhao c265bd5552 dm: clean up assert in virtio_audio.c
clean up assert from virtio_audio

Tracked-On: #3301
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-06-22 21:42:14 +08:00
Gao Junhao 14a93f7475 dm: clean up assert in virtio_input.c
clean up assert in virtio_input.c

Tracked-On: #3303
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-06-22 21:41:57 +08:00
Yan, Like 0a6baaf4d3 dm: samples: use stdio as vxworks console by default
Current launch script leaves stdio to OVMF console and, vxworks console to pty, so users
need to use additional tool like minicom to connect to pty device to use vxWorks.

To be more convinient, this commit changes the vxWorks to use the stdio by default, and OVMF
is not availabe by default.

Tracked-On: #3069
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-06-22 21:41:40 +08:00
Huihuang Shi e3ee9cf20e HV: fix expression is not boolean
MISRA-C standard requires the type of result of expression in if/while pattern shall be boolean.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2019-06-21 09:04:44 +08:00
Yuan Liu 5cbda22d29 dm: virtio_gpio: clean up assert
This patch is to clean up assert from virtio-gpio

Tracked-On: #3252
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-06-20 22:25:11 +08:00
Yuan Liu 1e23c4dc41 dm: ioc: clean up assert
This patch is to clean up assert from ioc

Tracked-On: #3252
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-06-20 22:25:11 +08:00
Kaige Fu 8740232ad6 HV: Allow pause RTVM when its state is VM_CREATED
There are a lot of works to do between create_vm (HV will mark vm's state
as VM_CREATED at this stage) and vm_run (HV will mark vm's state as VM_STARTED),
like building mptable/acpi table, initializing mevent and vdevs. If there is
something goes wrong between create_vm and vm_run, the devicemodel will jumps
to the deinit process and will try to destroy the vm. For example, if the
vm_init_vdevs failed, the devicemodel will jumps to dev_fail and then destroy
the vm.

For normal vm in above situation, it is fine to destroy vm. And we can create and
start it next time. But for RTVM, we can't destroy the vm as the vm's state is
VM_CREATED. And we can only destroy vm when its state is VM_POWERING_OFF. So, the
vm will stay at VM_CREATED state and we will never have chance to destroy it.
Consequently, we can't create and start the vm next time.

This patch fixes it by allowing to pause and then destroy RTVM when its state is VM_CREATED.

Tracked-On: #3069
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-06-20 22:24:38 +08:00
Shuo A Liu db7e7f1c44 dm: platform: clean up assert() for some platform devices
Tracked-On: #3252
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
2019-06-20 11:21:51 +08:00
Shuo A Liu 1b7995387d dm: pcidev: clean up assert() for some pci devices
Tracked-On: #3252
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
2019-06-20 11:21:51 +08:00
Shuo A Liu 2b3dedfb9b dm: pci: clean up assert() in pci core
Tracked-On: #3252
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
2019-06-20 11:21:51 +08:00
Yuan Liu f8934df355 HV: implement wbinvd instruction emulation
wbinvd is used to write back all modified cache lines in the processor's
internal cache to main memory and invalidates(flushes) the internal caches.

Using clflushopt instructions to emulate wbinvd to flush each
guest vm memory, if CLFLUSHOPT is not supported, boot will fail.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-06-20 09:32:55 +08:00
Yuan Liu ea699af861 HV: Add has_rt_vm API
The has_rt_vm walk through all VMs to check RT VM flag and if
there is no any RT VM, then return false otherwise return true.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2019-06-20 09:32:55 +08:00