Nicolas Pitre 530b593275 arch: riscv: apply CONFIG_RISCV_MCAUSE_EXCEPTION_MASK to FPU code ... Some implementations use bits outside of the mcause mask for other purpose. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2024-05-14 09:32:39 +02:00
..
offsets	arch: riscv: print callee-saved-registers in fatal error	2024-04-24 15:57:40 -04:00
CMakeLists.txt	…
asm_macros.inc	…
coredump.c	arch: riscv: update coredump for 64BIT RISCV	2024-04-13 07:03:23 -04:00
cpu_idle.c	…
fatal.c	arch: riscv: print callee-saved-registers in fatal error	2024-04-24 15:57:40 -04:00
fpu.S	…
fpu.c	…
irq_manage.c	arch: riscv: irq_manage: support ISR_OFFSET in dynamic IRQs	2024-04-25 15:03:23 +02:00
irq_offload.c	…
isr.S	arch: riscv: apply CONFIG_RISCV_MCAUSE_EXCEPTION_MASK to FPU code	2024-05-14 09:32:39 +02:00
pmp.S	…
pmp.c	coding guidelines: comply with MISRA Rule 11.8	2024-05-09 10:28:44 +02:00
prep_c.c	…
reboot.c	…
reset.S	…
semihost.c	…
smp.c	kernel: rename Z_KERNEL_STACK_BUFFER to K_KERNEL_STACK_BUFFER	2024-03-27 19:27:10 -04:00
switch.S	…
thread.c	kernel: rename Z_THREAD_STACK_BUFFER to K_THREAD_STACK_BUFFER	2024-03-27 19:27:10 -04:00
tls.c	…
userspace.S	…
vector_table.ld	…