465 lines
10 KiB
Plaintext
465 lines
10 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include <arm/armv7-m.dtsi>
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#include <mem.h>
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#include <freq.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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clocks {
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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cpu-power-states = <&idle &suspend_to_ram>;
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};
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power-states {
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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/* As Apollo3blueplus datasheet, run_to_sleep and sleep_to_run
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* transition time are both lower than 1us, but considering
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* the software overhead we set a bigger value.
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*/
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min-residency-us = <100>;
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exit-latency-us = <5>;
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};
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suspend_to_ram: suspend_to_ram {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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/* As Apollo3blueplus datasheet, run_to_deepsleep transition time
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* is the software overhead 1us and deepsleep_to_run transition
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* time is about 25us,but considering the software overhead,
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* we set a bigger value.
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*/
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min-residency-us = <2000>;
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exit-latency-us = <125>;
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};
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};
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};
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/* TCM */
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tcm: tcm@10000000 {
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compatible = "zephyr,memory-region";
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reg = <0x10000000 0x10000>;
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zephyr,memory-region = "ITCM";
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};
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/* SRAM */
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sram0: memory@10010000 {
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compatible = "mmio-sram";
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reg = <0x10010000 0xB0000>;
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};
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xip0: memory@52000000 {
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compatible = "zephyr,memory-region";
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reg = <0x52000000 0x2000000>;
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zephyr,memory-region = "XIP0";
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};
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xip1: memory@54000000 {
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compatible = "zephyr,memory-region";
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reg = <0x54000000 0x2000000>;
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zephyr,memory-region = "XIP1";
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};
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xip2: memory@56000000 {
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compatible = "zephyr,memory-region";
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reg = <0x56000000 0x2000000>;
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zephyr,memory-region = "XIP2";
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};
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soc {
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compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
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flash: flash-controller@c000 {
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compatible = "ambiq,flash-controller";
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reg = <0x0000c000 0x1f4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* Flash region */
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flash0: flash@c000 {
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compatible = "soc-nv-flash";
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reg = <0x0000c000 0x1f4000>;
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};
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};
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pwrcfg: pwrcfg@40021000 {
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compatible = "ambiq,pwrctrl";
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reg = <0x40021000 0x400>;
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#pwrcfg-cells = <2>;
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};
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stimer0: stimer@40008140 {
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compatible = "ambiq,stimer";
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reg = <0x40008140 0x80>;
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interrupts = <23 0>;
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status = "okay";
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};
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counter0: counter@40008000 {
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compatible = "ambiq,counter";
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reg = <0x40008000 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter1: counter@40008020 {
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compatible = "ambiq,counter";
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reg = <0x40008020 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter2: counter@40008040 {
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compatible = "ambiq,counter";
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reg = <0x40008040 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter3: counter@40008060 {
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compatible = "ambiq,counter";
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reg = <0x40008060 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter4: counter@40008080 {
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compatible = "ambiq,counter";
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reg = <0x40008080 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter5: counter@400080a0 {
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compatible = "ambiq,counter";
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reg = <0x400080A0 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter6: counter@400080c0 {
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compatible = "ambiq,counter";
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reg = <0x400080C0 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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counter7: counter@400080e0 {
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compatible = "ambiq,counter";
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reg = <0x400080E0 0x20>;
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interrupts = <14 0>;
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clock-frequency = <DT_FREQ_M(3)>;
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clk-source = <2>;
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status = "disabled";
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};
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uart0: uart@4001c000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001c000 0x1000>;
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interrupts = <15 0>;
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interrupt-names = "UART0";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
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zephyr,pm-device-runtime-auto;
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};
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uart1: uart@4001d000 {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <0x4001d000 0x1000>;
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interrupts = <16 0>;
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interrupt-names = "UART1";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
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zephyr,pm-device-runtime-auto;
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};
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spid0: spi@50000100 {
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compatible = "ambiq,spid";
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reg = <0x50000100 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <4 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0>;
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zephyr,pm-device-runtime-auto;
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};
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spi0: spi@50004000 {
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reg = <0x50004000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <6 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
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zephyr,pm-device-runtime-auto;
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};
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spi1: spi@50005000 {
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reg = <0x50005000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <7 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
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zephyr,pm-device-runtime-auto;
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};
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spi2: spi@50006000 {
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reg = <0x50006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
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zephyr,pm-device-runtime-auto;
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};
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spi3: spi@50007000 {
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reg = <0x50007000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <9 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
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zephyr,pm-device-runtime-auto;
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};
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spi4: spi@50008000 {
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reg = <0x50008000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <10 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
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zephyr,pm-device-runtime-auto;
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};
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spi5: spi@50009000 {
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reg = <0x50009000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
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zephyr,pm-device-runtime-auto;
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};
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i2c0: i2c@50004000 {
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reg = <0x50004000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <6 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
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zephyr,pm-device-runtime-auto;
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};
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i2c1: i2c@50005000 {
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reg = <0x50005000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <7 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
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zephyr,pm-device-runtime-auto;
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};
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i2c2: i2c@50006000 {
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reg = <0x50006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
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zephyr,pm-device-runtime-auto;
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};
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i2c3: i2c@50007000 {
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reg = <0x50007000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <9 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
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zephyr,pm-device-runtime-auto;
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};
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i2c4: i2c@50008000 {
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reg = <0x50008000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <10 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
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zephyr,pm-device-runtime-auto;
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};
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i2c5: i2c@50009000 {
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reg = <0x50009000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11 0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
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zephyr,pm-device-runtime-auto;
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};
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adc0: adc@50010000 {
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reg = <0x50010000 0x400>;
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interrupts = <18 0>;
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interrupt-names = "ADC";
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channel-count = <10>;
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internal-vref-mv = <1500>;
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status = "disabled";
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#io-channel-cells = <1>;
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ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
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};
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mspi0: mspi@50014000 {
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compatible = "ambiq,mspi-controller";
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reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
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clock-frequency = <48000000>;
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interrupts = <20 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
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};
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mspi1: mspi@50015000 {
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compatible = "ambiq,mspi-controller";
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reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
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clock-frequency = <48000000>;
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interrupts = <32 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
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};
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mspi2: mspi@50016000 {
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compatible = "ambiq,mspi-controller";
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clock-frequency = <48000000>;
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reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
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interrupts = <33 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
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};
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bleif: spi@5000c000 {
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compatible = "ambiq,spi-bleif";
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reg = <0x5000c000 0x414>;
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interrupts = <12 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
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bt_hci_apollo: bt-hci@0 {
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compatible = "ambiq,bt-hci-spi";
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spi-max-frequency = <DT_FREQ_M(6)>;
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reg = <0>;
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};
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};
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pinctrl: pin-controller@40010000 {
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compatible = "ambiq,apollo3-pinctrl";
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reg = <0x40010000 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio: gpio@40010000 {
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compatible = "ambiq,gpio";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0_31 0x0 0x0
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0x20 0x0 &gpio32_63 0x0 0x0
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0x40 0x0 &gpio64_95 0x0 0x0
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>;
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reg = <0x40010000>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ranges;
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gpio0_31: gpio0_31@0 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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interrupts = <13 0>;
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status = "disabled";
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};
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gpio32_63: gpio32_63@20 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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interrupts = <13 0>;
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status = "disabled";
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};
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gpio64_95: gpio64_95@40 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40>;
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interrupts = <13 0>;
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status = "disabled";
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ngpios = <10>;
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};
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};
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};
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wdt0: watchdog@40024000 {
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compatible = "ambiq,watchdog";
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reg = <0x40024000 0x400>;
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interrupts = <1 0>;
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clock-frequency = <16>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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