ecf308e8de
This commit adjusts the sizes of the two PLIC nodes AE350 defines: * `plic0` size is changed from `0x04000000` to `0x02000000` * `plic_sw` size is changed from `0x04000000` to `0x00400000` Without these change, `plic0` address space would overlap with `plic_sw`, and with other memory-mapped peripherals. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> |
||
|---|---|---|
| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| Kconfig | ||
| binding-template.yaml | ||