76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
/*
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* Copyright (c) 2023 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */
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};
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sram1: memory1@40000 {
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compatible = "mmio-sram";
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reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(400)>;
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#clock-cells = <0>;
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};
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pinctrl: pinctrl@4084000 {
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compatible = "ti,k3-pinctrl";
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reg = <0x04084000 0x88>;
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status = "okay";
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};
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uart0: serial@4a00000 {
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compatible = "ns16550";
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reg = <0x04a00000 0x200>;
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interrupts = <24 4>;
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interrupt-parent = <&nvic>;
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clock-frequency = <DT_FREQ_M(48)>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio0: gpio@4201010 {
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compatible = "ti,davinci-gpio";
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reg = <0x4201010 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&systick {
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status = "okay";
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};
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