553 lines
12 KiB
Plaintext
553 lines
12 KiB
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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cpu-power-states = <&idle &suspend_to_ram>;
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};
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power-states {
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <1000000>;
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};
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suspend_to_ram: suspend_to_ram {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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min-residency-us = <2000000>;
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};
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};
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};
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flash0: flash@e0000 {
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reg = <0x000E0000 0x38000>;
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};
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sram0: memory@118000 {
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compatible = "mmio-sram";
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reg = <0x00118000 0x8000>;
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};
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aliases {
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i2c-smb-0 = &i2c_smb_0;
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i2c-smb-1 = &i2c_smb_1;
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i2c-smb-2 = &i2c_smb_2;
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i2c-smb-3 = &i2c_smb_3;
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i2c-smb-4 = &i2c_smb_4;
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};
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soc {
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ecs: ecs@4000fc00 {
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compatible = "microchip,xec-ecs";
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reg = <0x4000fc00 0x200>;
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};
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pcr: pcr@40080100 {
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compatible = "microchip,xec-pcr";
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reg = <0x40080100 0x100 0x4000a400 0x100>;
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reg-names = "pcrr", "vbatr";
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core-clock-div = <1>;
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/* MEC15xx requires both sources to be the same */
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pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
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periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
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clk32kmon-period-min = <1435>;
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clk32kmon-period-max = <1495>;
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clk32kmon-duty-cycle-var-max = <132>;
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clk32kmon-valid-min = <4>;
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xtal-enable-delay-ms = <300>;
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pll-lock-timeout-ms = <30>;
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#clock-cells = <3>;
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};
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ecia: ecia@4000e000 {
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reg = <0x4000e000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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girq23: girq23@12c {
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reg = <0x12c 0x14>;
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interrupts = <14 0>;
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girq-id = <15>;
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sources = <0 1 2 4 5 10 16 17>;
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status = "disabled";
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};
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};
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pinctrl: pin-controller@40081000 {
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compatible = "microchip,xec-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40081000 0x1000>;
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gpio_000_036: gpio@40081000 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081000 0x80 0x40081300 0x04
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0x40081380 0x04 0x400813fc 0x04>;
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interrupts = <3 2>;
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gpio-controller;
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port-id = <0>;
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girq-id = <11>;
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#gpio-cells=<2>;
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};
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gpio_040_076: gpio@40081080 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081080 0x80 0x40081304 0x04
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0x40081384 0x04 0x400813f8 0x4>;
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interrupts = <2 2>;
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gpio-controller;
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port-id = <1>;
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girq-id = <10>;
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#gpio-cells=<2>;
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};
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gpio_100_136: gpio@40081100 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081100 0x80 0x40081308 0x04
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0x40081388 0x04 0x400813f4 0x04>;
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gpio-controller;
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interrupts = <1 2>;
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port-id = <2>;
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girq-id = <9>;
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#gpio-cells=<2>;
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};
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gpio_140_176: gpio@40081180 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081180 0x80 0x4008130c 0x04
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0x4008138c 0x04 0x400813f0 0x04>;
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gpio-controller;
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interrupts = <0 2>;
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port-id = <3>;
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girq-id = <8>;
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#gpio-cells=<2>;
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};
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gpio_200_236: gpio@40081200 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081200 0x80 0x40081310 0x04
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0x40081390 0x04 0x400813ec 0x04>;
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gpio-controller;
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interrupts = <4 2>;
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port-id = <4>;
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girq-id = <12>;
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#gpio-cells=<2>;
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};
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gpio_240_276: gpio@40081280 {
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compatible = "microchip,xec-gpio";
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reg = < 0x40081280 0x80 0x40081314 0x04
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0x40081394 0x04 0x400813e8 0x04>;
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gpio-controller;
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interrupts = <17 2>;
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port-id = <5>;
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girq-id = <26>;
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#gpio-cells=<2>;
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};
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};
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rtimer: timer@40007400 {
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compatible = "microchip,xec-rtos-timer";
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reg = <0x40007400 0x10>;
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interrupts = <111 0>;
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girqs = <23 10>;
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};
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bbram: bb-ram@4000a800 {
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compatible = "microchip,xec-bbram";
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reg = <0x4000a800 0x80>;
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reg-names = "memory";
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};
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wdog: watchdog@40000400 {
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compatible = "microchip,xec-watchdog";
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reg = <0x40000400 0x400>;
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interrupts = <171 0>;
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girqs = <21 2>;
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pcrs = <1 9>;
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};
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uart0: uart@400f2400 {
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compatible = "microchip,xec-uart";
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reg = <0x400f2400 0x400>;
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interrupts = <40 0>;
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clock-frequency = <1843200>;
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current-speed = <38400>;
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girqs = <15 0>;
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pcrs = <2 1>;
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ldn = <9>;
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status = "disabled";
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};
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uart1: uart@400f2800 {
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compatible = "microchip,xec-uart";
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reg = <0x400f2800 0x400>;
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interrupts = <41 0>;
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clock-frequency = <1843200>;
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current-speed = <38400>;
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girqs = <15 1>;
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pcrs = <2 2>;
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ldn = <10>;
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status = "disabled";
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};
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uart2: uart@400f2c00 {
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compatible = "microchip,xec-uart";
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reg = <0x400f2c00 0x400>;
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interrupts = <44 0>;
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clock-frequency = <1843200>;
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current-speed = <38400>;
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girqs = <15 4>;
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pcrs = <2 28>;
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ldn = <11>;
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status = "disabled";
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};
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i2c_smb_0: i2c@40004000 {
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compatible = "microchip,xec-i2c";
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reg = <0x40004000 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <20 1>;
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pcrs = <1 10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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girq = <13>;
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girq-bit = <0>;
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};
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i2c_smb_1: i2c@40004400 {
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compatible = "microchip,xec-i2c";
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reg = <0x40004400 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <21 1>;
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pcrs = <3 13>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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girq = <13>;
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girq-bit = <1>;
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};
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i2c_smb_2: i2c@40004800 {
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compatible = "microchip,xec-i2c";
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reg = <0x40004800 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <22 1>;
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pcrs = <3 14>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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girq = <13>;
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girq-bit = <2>;
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};
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i2c_smb_3: i2c@40004c00 {
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compatible = "microchip,xec-i2c";
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reg = <0x40004C00 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <23 1>;
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pcrs = <3 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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girq = <13>;
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girq-bit = <3>;
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};
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i2c_smb_4: i2c@40005000 {
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compatible = "microchip,xec-i2c";
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reg = <0x40005000 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <158 1>;
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pcrs = <3 20>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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girq = <13>;
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girq-bit = <4>;
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};
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espi0: espi@400f3400 {
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compatible = "microchip,xec-espi";
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reg = <0x400f3400 0x400>;
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interrupts = <11 3>, <15 3>, <7 3>, <16 3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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espi_saf0: espi@40008000 {
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compatible = "microchip,xec-espi-saf";
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reg = < 0x40008000 0x400
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0x40070000 0x400
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0x40071000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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timer0: timer@40000c00 {
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compatible = "microchip,xec-timer";
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clock-frequency = <48000000>;
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reg = <0x40000c00 0x20>;
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interrupts = <136 0>;
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max-value = <0xFFFF>;
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prescaler = <0>;
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status = "disabled";
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girqs = <23 0>;
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pcrs = <1 30>;
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};
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timer1: timer@40000c20 {
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compatible = "microchip,xec-timer";
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clock-frequency = <48000000>;
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reg = <0x40000c20 0x20>;
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interrupts = <137 0>;
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max-value = <0xFFFF>;
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prescaler = <0>;
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status = "disabled";
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girqs = <23 1>;
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pcrs = <1 31>;
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};
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/*
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* NOTE 1: timers 2 and 3 not implemented in MEC152x.
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* NOTE 2: When RTOS timer used as kernel timer, timer4 used
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* to provide high speed busy wait counter. Keep disabled to
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* prevent counter driver from claiming it.
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*/
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timer4: timer@40000c80 {
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compatible = "microchip,xec-timer";
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clock-frequency = <48000000>;
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reg = <0x40000c80 0x20>;
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interrupts = <140 0>;
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max-value = <0xFFFFFFFF>;
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prescaler = <0>;
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girqs = <23 4>;
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pcrs = <3 23>;
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status = "disabled";
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};
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timer5: timer@40000ca0 {
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compatible = "microchip,xec-timer";
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clock-frequency = <48000000>;
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reg = <0x40000ca0 0x20>;
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interrupts = <141 0>;
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max-value = <0xFFFFFFFF>;
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prescaler = <0>;
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girqs = <23 5>;
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pcrs = <3 24>;
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};
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hibtimer0: timer@40009800 {
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reg = <0x40009800 0x20>;
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interrupts = <112 0>;
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girqs = <23 16>;
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};
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hibtimer1: timer@40009820 {
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reg = <0x40009820 0x20>;
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interrupts = <113 0>;
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girqs = <23 17>;
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};
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ps2_0: ps2@40009000 {
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compatible = "microchip,xec-ps2";
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reg = <0x40009000 0x40>;
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interrupts = <100 1>;
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girqs = <18 10>, <21 18>;
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pcrs = <3 5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ps2_1: ps2@40009040 {
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compatible = "microchip,xec-ps2";
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reg = <0x40009040 0x40>;
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interrupts = <101 1>;
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girqs = <18 11>, <21 21>;
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pcrs = <3 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm0: pwm@40005800 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005800 0x20>;
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pcrs = <1 4>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm1: pwm@40005810 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005810 0x20>;
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pcrs = <1 20>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm2: pwm@40005820 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005820 0x20>;
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pcrs = <1 21>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm3: pwm@40005830 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005830 0x20>;
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pcrs = <1 22>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm4: pwm@40005840 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005840 0x20>;
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pcrs = <1 23>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm5: pwm@40005850 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005850 0x20>;
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pcrs = <1 24>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm6: pwm@40005860 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005860 0x20>;
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pcrs = <1 25>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm7: pwm@40005870 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005870 0x20>;
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pcrs = <1 26>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm8: pwm@40005880 {
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compatible = "microchip,xec-pwm";
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reg = <0x40005880 0x20>;
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pcrs = <1 27>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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adc0: adc@40007c00 {
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compatible = "microchip,xec-adc";
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reg = <0x40007c00 0x90>;
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interrupts = <78 0>, <79 0>;
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girqs = <17 8>, <17 9>;
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pcrs = <3 3>;
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status = "disabled";
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#io-channel-cells = <1>;
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clktime = <32>;
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};
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kbd0: kbd@40009c00 {
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compatible = "microchip,xec-kbd";
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reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
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girqs = <21 25>;
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pcrs = <3 11>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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peci0: peci@40006400 {
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compatible = "microchip,xec-peci";
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reg = <0x40006400 0x80>;
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interrupts = <70 4>;
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girqs = <17 0>;
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pcrs = <1 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@40070000 {
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compatible = "microchip,xec-qmspi";
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reg = <0x40070000 0x400>;
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interrupts = <91 2>;
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clock-frequency = <12000000>;
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rxdma = <11>;
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txdma = <10>;
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lines = <1>;
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chip_select = <0>;
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dcsckon = <6>;
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dckcsoff = <4>;
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dldh = <6>;
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dcsda = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tach0: tach@40006000 {
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compatible = "microchip,xec-tach";
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reg = <0x40006000 0x10>;
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interrupts = <71 4>;
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girqs = <17 1>;
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pcrs = <1 2>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tach1: tach@40006010 {
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compatible = "microchip,xec-tach";
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reg = <0x40006010 0x10>;
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interrupts = <72 4>;
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girqs = <17 2>;
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pcrs = <1 11>;
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status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
tach2: tach@40006020 {
|
|
compatible = "microchip,xec-tach";
|
|
reg = <0x40006020 0x10>;
|
|
interrupts = <73 4>;
|
|
girqs = <17 3>;
|
|
pcrs = <1 12>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
tach3: tach@40006030 {
|
|
compatible = "microchip,xec-tach";
|
|
reg = <0x40006030 0x10>;
|
|
interrupts = <159 4>;
|
|
girqs = <17 4>;
|
|
pcrs = <1 13>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
bbled0: bbled@4000b800 {
|
|
reg = <0x4000b800 0x100>;
|
|
interrupts = <83 0>;
|
|
girqs = <17 13>;
|
|
pcrs = <3 16>;
|
|
status = "disabled";
|
|
};
|
|
bbled1: bbled@4000b900 {
|
|
reg = <0x4000b900 0x100>;
|
|
interrupts = <84 0>;
|
|
girqs = <17 14>;
|
|
pcrs = <3 17>;
|
|
status = "disabled";
|
|
};
|
|
bbled2: bbled@4000ba00 {
|
|
reg = <0x4000ba00 0x100>;
|
|
interrupts = <85 0>;
|
|
girqs = <17 15>;
|
|
pcrs = <3 18>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|
|
|
|
&systick {
|
|
status = "disabled";
|
|
};
|