183 lines
4.0 KiB
Plaintext
183 lines
4.0 KiB
Plaintext
/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/adc/gd32f3x0.h>
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#include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32f3x0.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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clock-frequency = <DT_FREQ_M(108)>;
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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rcu: reset-clock-controller@40021000 {
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compatible = "gd,gd32-rcu";
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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status = "okay";
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};
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};
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fmc: flash-controller@40022000 {
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compatible = "gd,gd32-flash-controller";
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reg = <0x40022000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
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write-block-size = <2>;
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max-erase-time-ms = <300>;
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page-size = <DT_SIZE_K(1)>;
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};
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};
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usart0: usart@40013800 {
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compatible = "gd,gd32-usart";
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reg = <0x40013800 0x400>;
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interrupts = <27 0>;
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clocks = <&cctl GD32_CLOCK_USART0>;
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resets = <&rctl GD32_RESET_USART0>;
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status = "disabled";
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};
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usart1: usart@40004400 {
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compatible = "gd,gd32-usart";
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reg = <0x40004400 0x400>;
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interrupts = <28 0>;
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clocks = <&cctl GD32_CLOCK_USART1>;
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resets = <&rctl GD32_RESET_USART1>;
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status = "disabled";
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};
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adc0: adc@40012400 {
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compatible = "gd,gd32-adc";
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reg = <0x40012400 0x400>;
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interrupts = <12 0>;
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rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
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clocks = <&cctl GD32_CLOCK_ADC>;
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resets = <&rctl GD32_RESET_ADC>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dma: dma@40020000 {
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compatible = "gd,gd32-dma";
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reg = <0x40020000 0x400>;
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interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
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clocks = <&cctl GD32_CLOCK_DMA>;
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dma-channels = <7>;
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#dma-cells = <2>;
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status = "disabled";
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};
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fwdgt: watchdog@40003000 {
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compatible = "gd,gd32-fwdgt";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdgt: watchdog@40002c00 {
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compatible = "gd,gd32-wwdgt";
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reg = <0x40002C00 0x400>;
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clocks = <&cctl GD32_CLOCK_WWDGT>;
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resets = <&rctl GD32_RESET_WWDGT>;
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interrupts = <0 0>;
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status = "disabled";
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};
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pinctrl: pin-controller@48000000 {
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compatible = "gd,gd32-pinctrl-af";
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reg = <0x48000000 0x1800>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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gpioa: gpio@48000000 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOA>;
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resets = <&rctl GD32_RESET_GPIOA>;
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status = "disabled";
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};
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gpiob: gpio@48000400 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOB>;
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resets = <&rctl GD32_RESET_GPIOB>;
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status = "disabled";
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};
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gpioc: gpio@48000800 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOC>;
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resets = <&rctl GD32_RESET_GPIOC>;
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status = "disabled";
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};
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gpiod: gpio@48000c00 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOD>;
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resets = <&rctl GD32_RESET_GPIOD>;
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status = "disabled";
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};
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gpiof: gpio@48001400 {
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compatible = "gd,gd32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&cctl GD32_CLOCK_GPIOF>;
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resets = <&rctl GD32_RESET_GPIOF>;
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status = "disabled";
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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