136 lines
2.9 KiB
Plaintext
136 lines
2.9 KiB
Plaintext
/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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#include <zephyr/dt-bindings/dma/max32680_dma.h>
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&pinctrl {
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reg = <0x40008000 0x2400>;
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gpio2: gpio@40080400 {
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reg = <0x40080400 0x200>;
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compatible = "adi,max32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <26 0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
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status = "disabled";
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};
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gpio3: gpio@40080600 {
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reg = <0x40080600 0x200>;
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compatible = "adi,max32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <54 0>;
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status = "disabled";
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};
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};
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/ {
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soc {
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sram1: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(32)>;
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};
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sram2: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(48)>;
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};
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sram3: memory@2001c000 {
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compatible = "mmio-sram";
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reg = <0x2001c000 DT_SIZE_K(16)>;
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};
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uart3: serial@40081400 {
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compatible = "adi,max32-uart";
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reg = <0x40081400 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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interrupts = <88 0>;
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status = "disabled";
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
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dma-channels = <4>;
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status = "disabled";
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#dma-cells = <2>;
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};
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wdt1: watchdog@40080800 {
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compatible = "adi,max32-watchdog";
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reg = <0x40080800 0x400>;
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interrupts = <57 0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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status = "disabled";
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};
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spi0: spi@400be000 {
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compatible = "adi,max32-spi";
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reg = <0x400be000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
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interrupts = <56 0>;
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status = "disabled";
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};
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spi1: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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lptimer0: timer@40080c00 {
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compatible = "adi,max32-timer";
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reg = <0x40080c00 0x400>;
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interrupts = <9 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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prescaler = <1>;
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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lptimer1: timer@40081000 {
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compatible = "adi,max32-timer";
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reg = <0x40081000 0x400>;
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interrupts = <10 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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prescaler = <1>;
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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w1: w1@4003d000 {
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compatible = "adi,max32-w1";
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reg = <0x4003d000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
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interrupts = <67 0>;
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status = "disabled";
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};
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};
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};
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