178 lines
3.8 KiB
Plaintext
178 lines
3.8 KiB
Plaintext
/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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#include <zephyr/dt-bindings/dma/max32672_dma.h>
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(16)>;
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};
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&clk_inro {
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clock-frequency = <DT_FREQ_K(80)>;
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};
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&i2c2 {
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
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};
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/delete-node/ &clk_iso;
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&adc {
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compatible = "adi,max32-adc-sar", "adi,max32-adc";
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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clock-divider = <16>;
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channel-count = <16>;
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track-count = <4>;
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idle-count = <0>;
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vref-mv = <1250>;
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resolution = <12>;
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};
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/* MAX32672 extra peripherals. */
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/ {
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soc {
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sram1: memory@20004000 {
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compatible = "mmio-sram";
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reg = <0x20004000 DT_SIZE_K(16)>;
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};
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sram2: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(64)>;
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};
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sram3: memory@20018000 {
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compatible = "mmio-sram";
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reg = <0x20018000 DT_SIZE_K(64)>;
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};
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sram4: memory@20028000 {
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compatible = "mmio-sram";
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reg = <0x20028000 DT_SIZE_K(4)>;
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};
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sram5: memory@20029000 {
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compatible = "mmio-sram";
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reg = <0x20029000 DT_SIZE_K(4)>;
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};
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sram6: memory@2002a000 {
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compatible = "mmio-sram";
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reg = <0x2002a000 DT_SIZE_K(16)>;
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};
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sram7: memory@2002e000 {
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compatible = "mmio-sram";
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reg = <0x2002e000 DT_SIZE_K(16)>;
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};
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flc1: flash_controller@40029400 {
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compatible = "adi,max32-flash-controller";
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reg = <0x40029400 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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flash1: flash@10080000 {
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compatible = "soc-nv-flash";
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reg = <0x10080000 DT_SIZE_K(512)>;
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write-block-size = <16>;
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erase-block-size = <8192>;
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};
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};
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uart3: serial@40145000 {
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compatible = "adi,max32-uart";
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reg = <0x40145000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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interrupts = <88 0>;
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status = "disabled";
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
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<72 0>, <73 0>, <74 0>, <75 0>;
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dma-channels = <12>;
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status = "disabled";
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#dma-cells = <2>;
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};
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wdt1: watchdog@40003400 {
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compatible = "adi,max32-watchdog";
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reg = <0x40003400 0x400>;
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interrupts = <57 0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 5>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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status = "disabled";
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};
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spi0: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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spi1: spi@40047000 {
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compatible = "adi,max32-spi";
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reg = <0x40047000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
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interrupts = <17 0>;
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status = "disabled";
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};
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spi2: spi@40048000 {
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compatible = "adi,max32-spi";
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reg = <0x40048000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
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interrupts = <18 0>;
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status = "disabled";
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};
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lptimer0: timer@40114000 {
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compatible = "adi,max32-timer";
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reg = <0x40114000 0x1000>;
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interrupts = <9 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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prescaler = <1>;
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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lptimer1: timer@40115000 {
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compatible = "adi,max32-timer";
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reg = <0x40115000 0x1000>;
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interrupts = <10 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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prescaler = <1>;
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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};
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};
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