179 lines
3.7 KiB
Plaintext
179 lines
3.7 KiB
Plaintext
/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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&clk_ipo {
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clock-frequency = <DT_FREQ_M(96)>;
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};
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&uart0 {
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/delete-property/ clock-source;
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};
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&uart1 {
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/delete-property/ clock-source;
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};
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&uart2 {
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/delete-property/ clock-source;
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};
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/* MAX32666 extra peripherals. */
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/ {
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soc {
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sram1: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(32)>;
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};
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sram2: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram3: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(64)>;
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};
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sram4: memory@20030000 {
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compatible = "mmio-sram";
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reg = <0x20030000 DT_SIZE_K(128)>;
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};
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sram5: memory@20050000 {
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compatible = "mmio-sram";
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reg = <0x20050000 DT_SIZE_K(128)>;
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};
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sram6: memory@20070000 {
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compatible = "mmio-sram";
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reg = <0x20070000 DT_SIZE_K(8)>;
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};
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sram7: memory@20072000 {
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compatible = "mmio-sram";
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reg = <0x20072000 DT_SIZE_K(8)>;
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};
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sram8: memory@20074000 {
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compatible = "mmio-sram";
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reg = <0x20074000 DT_SIZE_K(16)>;
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};
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sram9: memory@20078000 {
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compatible = "mmio-sram";
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reg = <0x20078000 DT_SIZE_K(16)>;
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};
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sram10: memory@2007c000 {
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compatible = "mmio-sram";
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reg = <0x2007c000 DT_SIZE_K(32)>;
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};
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sram11: memory@20084000 {
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compatible = "mmio-sram";
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reg = <0x20084000 DT_SIZE_K(32)>;
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};
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flc1: flash_controller@40029400 {
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compatible = "adi,max32-flash-controller";
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reg = <0x40029400 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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flash1: flash@10080000 {
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compatible = "soc-nv-flash";
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reg = <0x10080000 DT_SIZE_K(512)>;
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write-block-size = <16>;
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erase-block-size = <8192>;
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};
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
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dma-channels = <8>;
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status = "disabled";
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#dma-cells = <2>;
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};
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dma1: dma@40035000 {
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compatible = "adi,max32-dma";
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reg = <0x40035000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
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interrupts = <72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
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dma-channels = <8>;
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status = "disabled";
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#dma-cells = <2>;
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};
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spi0: spi@400be000 {
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compatible = "adi,max32-spi";
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reg = <0x400be000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 14>;
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interrupts = <56 0>;
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status = "disabled";
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};
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spi1: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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spi2: spi@40047000 {
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compatible = "adi,max32-spi";
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reg = <0x40047000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
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interrupts = <17 0>;
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status = "disabled";
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};
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timer4: timer@40014000 {
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compatible = "adi,max32-timer";
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reg = <0x40014000 0x1000>;
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interrupts = <9 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 19>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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prescaler = <1>;
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};
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timer5: timer@40015000 {
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compatible = "adi,max32-timer";
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reg = <0x40015000 0x1000>;
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interrupts = <10 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 20>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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prescaler = <1>;
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};
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w1: w1@4003d000 {
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compatible = "adi,max32-w1";
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reg = <0x4003d000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
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interrupts = <67 0>;
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status = "disabled";
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};
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};
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};
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