zephyr/include/arch/riscv32/pulpino
Andrew Boie 506f15c381 interrupts: simplify position of sw ISR table
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.

The table will be placed in RAM if dynamic interrupts are
enabled.

A dedicated section is used, as this data must not move
in between build phases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
..
asm_inline.h headers: Fix headers across the project 2018-09-17 15:49:26 -04:00
asm_inline_gcc.h headers: Fix headers across the project 2018-09-17 15:49:26 -04:00
linker.ld interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00