260 lines
6.1 KiB
Plaintext
260 lines
6.1 KiB
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_rt1040.dtsi>
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#include "mimxrt1040_evk-pinctrl.dtsi"
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "NXP MIMXRT1040-EVK board";
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compatible = "nxp,mimxrt1042";
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aliases {
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led0 = &green_led;
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sw0 = &user_button;
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pwm-0 = &flexpwm1_pwm3;
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accel0 = &fxls8974;
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};
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chosen {
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zephyr,sram = &sdram0;
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zephyr,itcm = &itcm;
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zephyr,dtcm = &dtcm;
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,flash = &w25q64jvssiq;
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zephyr,flash-controller = &w25q64jvssiq;
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zephyr,code-partition = &slot0_partition;
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zephyr,uart-mcumgr = &lpuart1;
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zephyr,bt-hci = &bt_hci_uart;
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};
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sdram0: memory@80000000 {
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/* Winbond W9825G6KH SDRAM */
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(32)>;
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};
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/*
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* This node describes the GPIO pins of the parallel FPC interface,
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* This interface is standard to several NXP EVKs, and is used with
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* several parallel LCD displays (available as zephyr shields)
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*/
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nxp_parallel_lcd_connector: parallel-connector {
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compatible = "nxp,parallel-lcd-connector";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */
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};
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/*
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* This node describes the GPIO pins of the I2C display FPC interface,
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* This interface is standard to several NXP EVKs, and is used with
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* several parallel LCD displays (available as zephyr shields)
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*/
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nxp_i2c_touch_fpc: i2c-touch-connector {
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compatible = "nxp,i2c-tsc-fpc";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <1 0 &gpio1 19 0>, /* Pin 2, LCD touch RST */
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<2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */
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};
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leds {
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compatible = "gpio-leds";
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green_led: led_0 {
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gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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label = "User LD1";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button: button_0 {
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label = "User SW8";
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gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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arduino_header: connector {
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compatible = "arduino-header-r3";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpio1 14 0>, /* A0 */
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<1 0 &gpio1 15 0>, /* A1 */
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<2 0 &gpio1 20 0>, /* A2 */
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<3 0 &gpio1 21 0>, /* A3 */
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<4 0 &gpio1 22 0>, /* A4 */
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<5 0 &gpio1 23 0>, /* A5 */
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<6 0 &gpio3 1 0>, /* D0 */
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<7 0 &gpio3 0 0>, /* D1 */
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<8 0 &gpio1 11 0>, /* D2 */
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<9 0 &gpio3 2 0>, /* D3 */
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<10 0 &gpio1 9 0>, /* D4 */
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<11 0 &gpio1 10 0>, /* D5 */
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<12 0 &gpio1 18 0>, /* D6 */
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<13 0 &gpio1 19 0>, /* D7 */
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<14 0 &gpio2 30 0>, /* D8 */
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<15 0 &gpio2 31 0>, /* D9 */
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<16 0 &gpio3 13 0>, /* D10 */
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<17 0 &gpio3 14 0>, /* D11 */
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<18 0 &gpio3 15 0>, /* D12 */
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<19 0 &gpio3 12 0>, /* D13 */
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<20 0 &gpio1 17 0>, /* D14 */
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<21 0 &gpio1 16 0>; /* D15 */
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};
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};
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&flexspi {
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status = "okay";
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reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
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/* Winbond external flash */
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w25q64jvssiq: w25q64jvssiq@0 {
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compatible = "nxp,imx-flexspi-nor";
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size = <(DT_SIZE_M(8) * 8)>;
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reg = <0>;
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spi-max-frequency = <133000000>;
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status = "okay";
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jedec-id = [ef 40 17];
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erase-block-size = <4096>;
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write-block-size = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 DT_SIZE_K(128)>;
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};
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/* The MCUBoot swap-move algorithm uses the last 2 sectors
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* of the primary slot0 for swap status and move.
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*/
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slot0_partition: partition@20000 {
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label = "image-0";
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reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
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};
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slot1_partition: partition@322000 {
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label = "image-1";
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reg = <0x00322000 DT_SIZE_M(3)>;
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};
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storage_partition: partition@622000 {
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label = "storage";
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reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
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};
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};
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};
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};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&pinmux_lpuart1>;
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pinctrl-1 = <&pinmux_lpuart1_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&flexpwm1_pwm3 {
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status = "okay";
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pinctrl-0 = <&pinmux_flexpwm1_pwm3>;
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pinctrl-names = "default";
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};
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&adc1 {
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status = "okay";
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pinctrl-0 = <&pinmux_adc1>;
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pinctrl-names = "default";
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};
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&lpspi1 {
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status = "okay";
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/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
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dmas = <&edma0 0 13>, <&edma0 1 14>;
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dma-names = "rx", "tx";
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pinctrl-0 = <&pinmux_lpspi1>;
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pinctrl-names = "default";
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};
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&edma0 {
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status = "okay";
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};
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&lpi2c1 {
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status = "okay";
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pinctrl-0 = <&pinmux_lpi2c1>;
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pinctrl-names = "default";
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};
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nxp_touch_i2c: &lpi2c1 {};
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zephyr_lcdif: &lcdif {
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pinctrl-0 = <&pinmux_lcdif>;
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pinctrl-names = "default";
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};
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lpi2c3: &lpi2c3 {
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pinctrl-0 = <&pinmux_lpi2c3>;
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pinctrl-names = "default";
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status = "okay";
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fxls8974: fxls8974@18 {
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compatible = "nxp,fxls8974";
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reg = <0x18>;
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status = "okay";
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/* Two zero ohm resistors (R115 and R122) isolate sensor
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* interrupt gpios from the soc and are unpopulated by default.
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* Note that if you populate them, they conflict with JTAG_TDO and
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* ethernet PHY interrupt signals.
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* int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
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* int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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*/
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};
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};
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/* GPT and Systick are enabled. If power management is enabled, the GPT
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* timer will be used instead of systick, as allows the core clock to
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* be gated.
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*/
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&gpt_hw_timer {
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status = "okay";
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};
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&systick {
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status = "okay";
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};
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m2_hci_uart: &lpuart3 {
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pinctrl-0 = <&pinmux_lpuart3_flowcontrol>;
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pinctrl-1 = <&pinmux_lpuart3_sleep>;
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pinctrl-names = "default", "sleep";
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bt_hci_uart: bt_hci_uart {
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compatible = "zephyr,bt-hci-uart";
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m2_bt_module {
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compatible = "nxp,bt-hci-uart";
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sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
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w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
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hci-operation-speed = <115200>;
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hw-flow-control;
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fw-download-primary-speed = <115200>;
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fw-download-secondary-speed = <3000000>;
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fw-download-secondary-flowcontrol;
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};
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};
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};
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&m2_hci_uart {
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status = "okay";
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current-speed = <115200>;
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};
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