/* * Copyright 2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include #include "mimxrt1040_evk-pinctrl.dtsi" #include / { model = "NXP MIMXRT1040-EVK board"; compatible = "nxp,mimxrt1042"; aliases { led0 = &green_led; sw0 = &user_button; pwm-0 = &flexpwm1_pwm3; accel0 = &fxls8974; }; chosen { zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,flash = &w25q64jvssiq; zephyr,flash-controller = &w25q64jvssiq; zephyr,code-partition = &slot0_partition; zephyr,uart-mcumgr = &lpuart1; zephyr,bt-hci = &bt_hci_uart; }; sdram0: memory@80000000 { /* Winbond W9825G6KH SDRAM */ device_type = "memory"; reg = <0x80000000 DT_SIZE_M(32)>; }; /* * This node describes the GPIO pins of the parallel FPC interface, * This interface is standard to several NXP EVKs, and is used with * several parallel LCD displays (available as zephyr shields) */ nxp_parallel_lcd_connector: parallel-connector { compatible = "nxp,parallel-lcd-connector"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ }; /* * This node describes the GPIO pins of the I2C display FPC interface, * This interface is standard to several NXP EVKs, and is used with * several parallel LCD displays (available as zephyr shields) */ nxp_i2c_touch_fpc: i2c-touch-connector { compatible = "nxp,i2c-tsc-fpc"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <1 0 &gpio1 19 0>, /* Pin 2, LCD touch RST */ <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ }; leds { compatible = "gpio-leds"; green_led: led_0 { gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; label = "User LD1"; }; }; gpio_keys { compatible = "gpio-keys"; user_button: button_0 { label = "User SW8"; gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; zephyr,code = ; }; }; arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = <0 0 &gpio1 14 0>, /* A0 */ <1 0 &gpio1 15 0>, /* A1 */ <2 0 &gpio1 20 0>, /* A2 */ <3 0 &gpio1 21 0>, /* A3 */ <4 0 &gpio1 22 0>, /* A4 */ <5 0 &gpio1 23 0>, /* A5 */ <6 0 &gpio3 1 0>, /* D0 */ <7 0 &gpio3 0 0>, /* D1 */ <8 0 &gpio1 11 0>, /* D2 */ <9 0 &gpio3 2 0>, /* D3 */ <10 0 &gpio1 9 0>, /* D4 */ <11 0 &gpio1 10 0>, /* D5 */ <12 0 &gpio1 18 0>, /* D6 */ <13 0 &gpio1 19 0>, /* D7 */ <14 0 &gpio2 30 0>, /* D8 */ <15 0 &gpio2 31 0>, /* D9 */ <16 0 &gpio3 13 0>, /* D10 */ <17 0 &gpio3 14 0>, /* D11 */ <18 0 &gpio3 15 0>, /* D12 */ <19 0 &gpio3 12 0>, /* D13 */ <20 0 &gpio1 17 0>, /* D14 */ <21 0 &gpio1 16 0>; /* D15 */ }; }; &flexspi { status = "okay"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; /* Winbond external flash */ w25q64jvssiq: w25q64jvssiq@0 { compatible = "nxp,imx-flexspi-nor"; size = <(DT_SIZE_M(8) * 8)>; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; jedec-id = [ef 40 17]; erase-block-size = <4096>; write-block-size = <1>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; /* The MCUBoot swap-move algorithm uses the last 2 sectors * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; }; slot1_partition: partition@322000 { label = "image-1"; reg = <0x00322000 DT_SIZE_M(3)>; }; storage_partition: partition@622000 { label = "storage"; reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; }; }; }; }; &lpuart1 { status = "okay"; current-speed = <115200>; pinctrl-0 = <&pinmux_lpuart1>; pinctrl-1 = <&pinmux_lpuart1_sleep>; pinctrl-names = "default", "sleep"; }; &flexpwm1_pwm3 { status = "okay"; pinctrl-0 = <&pinmux_flexpwm1_pwm3>; pinctrl-names = "default"; }; &adc1 { status = "okay"; pinctrl-0 = <&pinmux_adc1>; pinctrl-names = "default"; }; &lpspi1 { status = "okay"; /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ dmas = <&edma0 0 13>, <&edma0 1 14>; dma-names = "rx", "tx"; pinctrl-0 = <&pinmux_lpspi1>; pinctrl-names = "default"; }; &edma0 { status = "okay"; }; &lpi2c1 { status = "okay"; pinctrl-0 = <&pinmux_lpi2c1>; pinctrl-names = "default"; }; nxp_touch_i2c: &lpi2c1 {}; zephyr_lcdif: &lcdif { pinctrl-0 = <&pinmux_lcdif>; pinctrl-names = "default"; }; lpi2c3: &lpi2c3 { pinctrl-0 = <&pinmux_lpi2c3>; pinctrl-names = "default"; status = "okay"; fxls8974: fxls8974@18 { compatible = "nxp,fxls8974"; reg = <0x18>; status = "okay"; /* Two zero ohm resistors (R115 and R122) isolate sensor * interrupt gpios from the soc and are unpopulated by default. * Note that if you populate them, they conflict with JTAG_TDO and * ethernet PHY interrupt signals. * int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; * int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; */ }; }; /* GPT and Systick are enabled. If power management is enabled, the GPT * timer will be used instead of systick, as allows the core clock to * be gated. */ &gpt_hw_timer { status = "okay"; }; &systick { status = "okay"; }; m2_hci_uart: &lpuart3 { pinctrl-0 = <&pinmux_lpuart3_flowcontrol>; pinctrl-1 = <&pinmux_lpuart3_sleep>; pinctrl-names = "default", "sleep"; bt_hci_uart: bt_hci_uart { compatible = "zephyr,bt-hci-uart"; m2_bt_module { compatible = "nxp,bt-hci-uart"; sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; hci-operation-speed = <115200>; hw-flow-control; fw-download-primary-speed = <115200>; fw-download-secondary-speed = <3000000>; fw-download-secondary-flowcontrol; }; }; }; &m2_hci_uart { status = "okay"; current-speed = <115200>; };