zephyr/soc/xtensa
Pierre-Louis Bossart b871138fae soc/intel_adsp: fix typo in L1EXP definition
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.

Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2023-06-06 17:20:01 -04:00
..
esp32 soc: esp32: Fix linker scripts 2023-06-01 10:05:20 +02:00
esp32_net soc: kconfig: Add config for ESP32 family 2023-04-19 17:12:26 +02:00
esp32s2 soc: esp32: MCUboot support 2023-05-25 16:15:54 +02:00
esp32s3 soc: esp32: Update soc startup and cache init 2023-06-01 10:05:20 +02:00
intel_adsp soc/intel_adsp: fix typo in L1EXP definition 2023-06-06 17:20:01 -04:00
nxp_adsp soc: xtensa: nxp_adsp: Enable cache management API for NXP SoCs 2023-05-17 18:34:24 -04:00
sample_controller xtensa: linker: Use zephyr's convention for rodata 2022-11-17 15:44:48 +09:00
CMakeLists.txt