Gerard Marull-Paretas 47fba91367 soc: riscv: telink_b91: add missing init.h, devicetree.h ... File was including device.h for nothing, it needs init.h and devicetree.h instead. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2023-08-30 11:51:57 +02:00
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andes_v5	soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE	2023-07-17 10:10:31 +00:00
common	riscv: privileged: Add support for CLIC vectored mode	2023-06-17 07:48:52 -04:00
efinix-sapphire	soc: riscv: Add ability to use custom sys_io functions	2023-07-26 09:43:59 +02:00
gd32vf103	…
miv	…
mpfs	…
neorv32	boards: riscv: neorv32: Updates compatibility to neoverse v1.8.6	2023-07-11 18:19:55 +00:00
niosv	…
opentitan	riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE	2023-06-17 07:48:52 -04:00
sifive-freedom	…
starfive_jh71xx	…
telink_b91	soc: riscv: telink_b91: add missing init.h, devicetree.h	2023-08-30 11:51:57 +02:00
virt	…
CMakeLists.txt	…
Kconfig	riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE	2023-06-17 07:48:52 -04:00
Kconfig.defconfig	…
Kconfig.soc	…