Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.
Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.
Signed-off-by: Keith Packard <keithp@keithp.com>
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add support for INTEL FPGA Nios V/g RISC-V based Processors.
Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Gerard Marull-Paretas