122 lines
6.2 KiB
Verilog
122 lines
6.2 KiB
Verilog
module ghrd_10m50da_top (
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//Clock and Reset
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input wire clk_50,
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//input wire clk_ddr3_100_p,
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input wire fpga_reset_n,
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//QSPI
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output wire qspi_clk,
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inout wire[3:0] qspi_io,
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output wire qspi_csn,
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//ddr3
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//output wire [13:0] mem_a,
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//output wire [2:0] mem_ba,
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//inout wire [0:0] mem_ck,
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//inout wire [0:0] mem_ck_n,
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//output wire [0:0] mem_cke,
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//output wire [0:0] mem_cs_n,
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//output wire [0:0] mem_dm,
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//output wire [0:0] mem_ras_n,
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//output wire [0:0] mem_cas_n,
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//output wire [0:0] mem_we_n,
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//output wire mem_reset_n,
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///inout wire [7:0] mem_dq,
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//inout wire [0:0] mem_dqs,
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//inout wire [0:0] mem_dqs_n,
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//output wire [0:0] mem_odt,
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//i2c
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inout wire i2c_sda,
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inout wire i2c_scl,
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//spi
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input wire spi_miso,
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output wire spi_mosi,
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output wire spi_sclk,
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output wire spi_ssn,
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//16550 UART
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input wire uart_rx,
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output wire uart_tx,
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output wire [4:0] user_led
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);
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//Heart-beat counter
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reg [25:0] heart_beat_cnt;
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//DDR3 interface assignments
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//wire local_init_done;
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//wire local_cal_success;
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//wire local_cal_fail;
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//i2c interface
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wire i2c_serial_sda_in ;
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wire i2c_serial_scl_in ;
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wire i2c_serial_sda_oe ;
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wire i2c_serial_scl_oe ;
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assign i2c_serial_scl_in = i2c_scl;
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assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
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assign i2c_serial_sda_in = i2c_sda;
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assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
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//assign system_resetn = fpga_reset_n & local_init_done;
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// SoC sub-system module
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ghrd_10m50da ghrd_10m50da_inst (
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.clk_clk (clk_50),
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//.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
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.reset_reset_n (fpga_reset_n),
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//.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
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.ext_flash_qspi_pins_data (qspi_io),
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.ext_flash_qspi_pins_dclk (qspi_clk),
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.ext_flash_qspi_pins_ncs (qspi_csn),
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//.memory_mem_a (mem_a[12:0] ), // memory.mem_a
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//.memory_mem_ba (mem_ba ), // .mem_ba
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//.memory_mem_ck (mem_ck ), // .mem_ck
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//.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
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//.memory_mem_cke (mem_cke ), // .mem_cke
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//.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
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//.memory_mem_dm (mem_dm ), // .mem_dm
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//.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
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//.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
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//.memory_mem_we_n (mem_we_n ), // .mem_we_n
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//.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
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//.memory_mem_dq (mem_dq ), // .mem_dq
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//.memory_mem_dqs (mem_dqs ), // .mem_dqs
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//.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
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//.memory_mem_odt (mem_odt ), // .mem_odt
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//.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
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//.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
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//.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
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//i2c
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.i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
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.i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
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.i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
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.i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
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//spi
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.spi_0_external_MISO (spi_miso), // spi_0_external.MISO
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.spi_0_external_MOSI (spi_mosi), // .MOSI
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.spi_0_external_SCLK (spi_sclk), // .SCLK
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.spi_0_external_SS_n (spi_ssn), // .SS_n
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//pio
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.led_external_connection_export (user_led[3:0]),
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//16550 UART
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.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
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.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
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.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
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);
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//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
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//assign mem_a[13] = 1'b0;
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//Heart beat by 50MHz clock
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always @(posedge clk_50 or negedge fpga_reset_n)
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if (!fpga_reset_n)
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heart_beat_cnt <= 26'h0; //0x3FFFFFF
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else
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heart_beat_cnt <= heart_beat_cnt + 1'b1;
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assign user_led[4] = heart_beat_cnt[25];
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endmodule
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