211 lines
5.5 KiB
C
211 lines
5.5 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DRIVERS_ETHERNET_ETH_DW_PRIV_H_
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#define DRIVERS_ETHERNET_ETH_DW_PRIV_H_
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#ifdef CONFIG_PCI
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#include <pci/pci.h>
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#include <pci/pci_mgr.h>
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#endif /* CONFIG_PCI */
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#include <misc/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*eth_config_irq_t)(struct device *port);
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struct eth_config {
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u32_t irq_num;
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eth_config_irq_t config_func;
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#ifdef CONFIG_ETH_DW_SHARED_IRQ
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char *shared_irq_dev_name;
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#endif /* CONFIG_ETH_DW_SHARED_IRQ */
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};
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/* Refer to Intel Quark SoC X1000 Datasheet, Chapter 15 for more details on
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* Ethernet device operation.
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*
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* This driver puts the Ethernet device into a very simple and space-efficient
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* mode of operation. It only allocates a single packet descriptor for each of
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* the transmit and receive directions, computes checksums on the CPU, and
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* enables store-and-forward mode for both transmit and receive directions.
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*/
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/* Transmit descriptor */
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struct eth_tx_desc {
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/* First word of transmit descriptor */
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union {
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struct {
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/* Only valid in half-duplex mode. */
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u32_t deferred_bit : 1;
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u32_t err_underflow : 1;
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u32_t err_excess_defer : 1;
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u32_t coll_cnt_slot_num : 4;
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u32_t vlan_frm : 1;
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u32_t err_excess_coll : 1;
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u32_t err_late_coll : 1;
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u32_t err_no_carrier : 1;
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u32_t err_carrier_loss : 1;
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u32_t err_ip_payload : 1;
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u32_t err_frm_flushed : 1;
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u32_t err_jabber_tout : 1;
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/* OR of all other error bits. */
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u32_t err_summary : 1;
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u32_t err_ip_hdr : 1;
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u32_t tx_timestamp_stat : 1;
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u32_t vlan_ins_ctrl : 2;
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u32_t addr2_chained : 1;
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u32_t tx_end_of_ring : 1;
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u32_t chksum_ins_ctrl : 2;
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u32_t replace_crc : 1;
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u32_t tx_timestamp_en : 1;
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u32_t dis_pad : 1;
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u32_t dis_crc : 1;
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u32_t first_seg_in_frm : 1;
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u32_t last_seg_in_frm : 1;
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u32_t intr_on_complete : 1;
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/* When set, descriptor is owned by DMA. */
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u32_t own : 1;
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};
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u32_t tdes0;
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};
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/* Second word of transmit descriptor */
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union {
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struct {
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u32_t tx_buf1_sz : 13;
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u32_t : 3;
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u32_t tx_buf2_sz : 13;
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u32_t src_addr_ins_ctrl : 3;
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};
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u32_t tdes1;
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};
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/* Pointer to frame data buffer */
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u8_t *buf1_ptr;
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/* Unused, since this driver initializes only a single descriptor for each
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* direction.
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*/
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u8_t *buf2_ptr;
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};
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/* Transmit descriptor */
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struct eth_rx_desc {
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/* First word of receive descriptor */
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union {
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struct {
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u32_t ext_stat : 1;
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u32_t err_crc : 1;
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u32_t err_dribble_bit : 1;
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u32_t err_rx_mii : 1;
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u32_t err_rx_wdt : 1;
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u32_t frm_type : 1;
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u32_t err_late_coll : 1;
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u32_t giant_frm : 1;
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u32_t last_desc : 1;
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u32_t first_desc : 1;
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u32_t vlan_tag : 1;
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u32_t err_overflow : 1;
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u32_t length_err : 1;
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u32_t s_addr_filt_fail : 1;
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u32_t err_desc : 1;
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u32_t err_summary : 1;
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u32_t frm_len : 14;
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u32_t d_addr_filt_fail : 1;
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u32_t own : 1;
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};
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u32_t rdes0;
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};
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/* Second word of receive descriptor */
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union {
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struct {
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u32_t rx_buf1_sz : 13;
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u32_t : 1;
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u32_t addr2_chained : 1;
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u32_t rx_end_of_ring : 1;
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u32_t rx_buf2_sz : 13;
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u32_t : 2;
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u32_t dis_int_compl : 1;
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};
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u32_t rdes1;
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};
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/* Pointer to frame data buffer */
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u8_t *buf1_ptr;
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/* Unused, since this driver initializes only a single descriptor for each
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* direction.
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*/
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u8_t *buf2_ptr;
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};
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#define ETH_DW_MTU 1500
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/* Driver metadata associated with each Ethernet device */
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struct eth_runtime {
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u32_t base_addr;
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struct net_if *iface;
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#ifdef CONFIG_PCI
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struct pci_dev_info pci_dev;
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#endif /* CONFIG_PCI */
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/* Transmit descriptor */
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volatile struct eth_tx_desc tx_desc;
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/* Receive descriptor */
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volatile struct eth_rx_desc rx_desc;
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/* Receive DMA packet buffer */
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volatile u8_t rx_buf[ETH_DW_MTU];
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union {
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struct {
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u8_t bytes[6];
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u8_t pad[2];
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} __packed;
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u32_t words[2];
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} mac_addr;
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};
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#define MMC_DEFAULT_MASK 0xffffffff
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#define MAC_CONF_14_RMII_100M BIT(14)
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#define MAC_CONF_11_DUPLEX BIT(11)
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#define MAC_CONF_3_TX_EN BIT(3)
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#define MAC_CONF_2_RX_EN BIT(2)
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#define MAC_FILTER_4_PM BIT(4)
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#define STATUS_NORMAL_INT BIT(16)
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#define STATUS_RX_INT BIT(6)
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#define OP_MODE_25_RX_STORE_N_FORWARD BIT(25)
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#define OP_MODE_21_TX_STORE_N_FORWARD BIT(21)
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#define OP_MODE_13_START_TX BIT(13)
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#define OP_MODE_1_START_RX BIT(1)
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#define INT_ENABLE_NORMAL BIT(16)
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#define INT_ENABLE_RX BIT(6)
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#define REG_ADDR_MAC_CONF 0x0000
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#define REG_ADDR_MAC_FRAME_FILTER 0x0004
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#define REG_ADDR_MACADDR_HI 0x0040
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#define REG_ADDR_MACADDR_LO 0x0044
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#define REG_MMC_RX_INTR_MASK 0x010c
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#define REG_MMC_TX_INTR_MASK 0x0110
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#define REG_MMC_RX_IPC_INTR_MASK 0x0200
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#define REG_ADDR_TX_POLL_DEMAND 0x1004
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#define REG_ADDR_RX_POLL_DEMAND 0x1008
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#define REG_ADDR_RX_DESC_LIST 0x100C
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#define REG_ADDR_TX_DESC_LIST 0x1010
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#define REG_ADDR_STATUS 0x1014
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#define REG_ADDR_DMA_OPERATION 0x1018
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#define REG_ADDR_INT_ENABLE 0x101C
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#ifdef __cplusplus
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}
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#endif
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#endif /* DRIVERS_ETHERNET_ETH_DW_PRIV_H_ */
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