The main difference to how the previous driver operates, is that this
version has zero-copy transmission. The transmit DMA descriptor is
updated for every fragment that is transmitted from the driver.
Another difference in the transmission path is that this version won't
spin indefinitely while waiting for the DMA transfer to complete; an
arbitrary number of busy checks (20) will be performed, and then
the transmission thread will yield for as long as necessary to finish
the transfer.
These two changes should fix ZEP-472; since that issue was opened for
an older version of Zephyr with uIP, I did not bother going all the way
back to test.
This has been only tested with a Galileo board, using Shared IRQ.
Jira: ZEP-1652
Jira: ZEP-472
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Mutable driver state relocated from config_info to driver_info. This
driver supports PCI enumeration. We drop code that attempts to update
irq_num based on PCI enumeration because the interrupt found by PCI
enumeration must always be the same as the statically configured IRQ
number.
Change-Id: I5580b0ba95635696a825fe66dbf16259c54d5ba8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The ethernet driver generates a lot of spurious interrupts.
These spurious interrupts have two sources:
1) The Mac Management Counter (MMC) module generates a lot of interrupts
(GMI - bit 27 of the status register). Unfortunately the Interrupt
enable register doesn't allow us to enable/disable it (bit 27 is
reserved). Therefore the only way to mask this interrupt is to mask
all the MMC interrupts (register REG_MMC_RX_INTR_MASK,
REG_MMC_TX_INTR_MASK and REG_MMC_RX_IPC_INTR_MASK). By default
these interrupts are not masked.
2) The RX interrupt is not correctly acknowledged. According to the
datasheet, NIS is a sticky bit and must be cleared (by writing 1
to this bit) each time a corresponding bit, which causes NIS to
be set, is cleared.
Change-Id: I2033973849d87cddc328c65d0d4ad36b5a0c934e
Signed-off-by: Sebastien Griffoul <sebastien.griffoul@intel.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This patch adds a driver for a Synopsys DesignWare Ethernet MAC. The
driver uses interrupts to handle received frames, but it uses a
spinloop when transmitting to wait for the transmit descriptor to
become available. Transmission is coordinated by a fiber, so this
should not result in the system execution being blocked. Only a
single descriptor is allocated for each of the transmit and receive
directions to save memory and simplify the code. Another
simplification is that none of the offload capabilities of the
Ethernet device are used. The driver currently only supports a single
instance of the Ethernet MAC, which is consistent with the limitation
in the network stack that only a single network device is supported.
Change-Id: I013b3d439a76e8ff91a775516f7035841b040870
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
Leandro Pereira