zephyr/dts
Duy Nguyen 0a68d492e2 dts: renesas: Separate pll p q r into child node
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2024-11-05 10:54:28 -06:00
..
arc/synopsys drivers: spi: dw: define max-xfer-size 2024-01-20 13:11:42 +01:00
arm dts: renesas: Separate pll p q r into child node 2024-11-05 10:54:28 -06:00
arm64 soc: imx93: enable flexcan driver 2024-09-17 17:44:14 +01:00
bindings dts: renesas: Separate pll p q r into child node 2024-11-05 10:54:28 -06:00
common dts: nordic: nrf54h20: add power domain information 2024-11-01 12:10:12 -05:00
nios2/intel dts: nios2: intel: Fix unit and first address mismatch 2024-09-18 15:30:24 +02:00
posix
riscv dts/andes: adjust the sizes of PLIC nodes 2024-10-31 14:17:02 -05:00
sparc/gaisler soc/gr716a: Enable GPIO support on LEON GR716A 2024-07-29 14:27:15 +02:00
x86/intel dts: x86: intel: ish: Remove d0i1 and modify d0i2 2024-07-04 13:26:24 +02:00
xtensa pm: s/power-domain/power-domains and add power-domain-names 2024-10-18 17:45:21 +01:00
Kconfig dts: drop HAS_DTS 2023-10-20 12:18:17 -07:00
binding-template.yaml