96cadd1a9a
We have already done this on x86 and ARM. The policy is as follows: * IRQ priority levels starting at 0 all have the same semantics and do not have special properties. The priority level is either ignored on arches which do not support programmable priority levels, or lower priority levels take precedence over higher ones. * Special-case priorty levels are specified via flags, in which case the supplied priority level is ignored. Issue: ZEP-60 Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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.. | ||
Kconfig | ||
Makefile | ||
altera_avalon_timer.c | ||
arcv2_timer0.c | ||
cortex_m_systick.c | ||
cortex_m_systick_gdb.S | ||
hpet.c | ||
loapic_timer.c | ||
sys_clock_init.c |