67 lines
2.6 KiB
CMake
67 lines
2.6 KiB
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_cc_option(-mlongcalls)
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zephyr_library()
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zephyr_library_sources(
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cpu_idle.c
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fatal.c
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window_vectors.S
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xtensa_asm2_util.S
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irq_manage.c
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thread.c
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vector_handlers.c
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)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE xtensa_backtrace.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE debug_helpers_asm.S)
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zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
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zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
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zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c)
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zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
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zephyr_library_sources_ifdef(CONFIG_SMP smp.c)
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zephyr_library_sources_ifdef(
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CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK
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mem_manage.c
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)
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if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
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zephyr_library_sources(xcc_stubs.c)
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endif()
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add_subdirectory(startup)
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# This produces a preprocessed and regenerated (in the sense of gcc
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# -dM, supported by all Xtensa toolchains) core-isa.h file available
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# as "core-isa-dM.h". This can be easily parsed by non-C tooling.
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#
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# Note that this adds the SOC/HAL include directory explicitly, they
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# are the official places where we find core-isa.h. (Also that we
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# undefine __XCC_ because that compiler actually trips an error trying
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# to build this file to protect against mismatched versions.)
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set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.h)
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set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
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file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
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add_custom_command(OUTPUT ${CORE_ISA_DM}
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COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
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-I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
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-I${SOC_DIR}/${ARCH}/${SOC_PATH}
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${CORE_ISA_IN} -o ${CORE_ISA_DM})
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# Generates a list of device-specific scratch register choices
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set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zsr.h)
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add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
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COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
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$<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
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${CORE_ISA_DM} ${ZSR_H})
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add_custom_target(zsr_h DEPENDS ${ZSR_H})
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add_dependencies(zephyr_interface zsr_h)
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