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zephyr/arch/xtensa/core/CMakeLists.txt

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
# SPDX-License-Identifier: Apache-2.0
Introduce cmake-based rewrite of KBuild Introducing CMake is an important step in a larger effort to make Zephyr easy to use for application developers working on different platforms with different development environment needs. Simplified, this change retains Kconfig as-is, and replaces all Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild offers is replaced by a set of CMake extentions. These extentions have either provided simple one-to-one translations of KBuild features or introduced new concepts that replace KBuild concepts. This is a breaking change for existing test infrastructure and build scripts that are maintained out-of-tree. But for FW itself, no porting should be necessary. For users that just want to continue their work with minimal disruption the following should suffice: Install CMake 3.8.2+ Port any out-of-tree Makefiles to CMake. Learn the absolute minimum about the new command line interface: $ cd samples/hello_world $ mkdir build && cd build $ cmake -DBOARD=nrf52_pca10040 .. $ cd build $ make PR: zephyrproject-rtos#4692 docs: http://docs.zephyrproject.org/getting_started/getting_started.html Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-10-27 21:43:34 +08:00
zephyr_cc_option(-mlongcalls)
headers: Refactor kernel and arch headers. This commit refactors kernel and arch headers to establish a boundary between private and public interface headers. The refactoring strategy used in this commit is detailed in the issue This commit introduces the following major changes: 1. Establish a clear boundary between private and public headers by removing "kernel/include" and "arch/*/include" from the global include paths. Ideally, only kernel/ and arch/*/ source files should reference the headers in these directories. If these headers must be used by a component, these include paths shall be manually added to the CMakeLists.txt file of the component. This is intended to discourage applications from including private kernel and arch headers either knowingly and unknowingly. - kernel/include/ (PRIVATE) This directory contains the private headers that provide private kernel definitions which should not be visible outside the kernel and arch source code. All public kernel definitions must be added to an appropriate header located under include/. - arch/*/include/ (PRIVATE) This directory contains the private headers that provide private architecture-specific definitions which should not be visible outside the arch and kernel source code. All public architecture- specific definitions must be added to an appropriate header located under include/arch/*/. - include/ AND include/sys/ (PUBLIC) This directory contains the public headers that provide public kernel definitions which can be referenced by both kernel and application code. - include/arch/*/ (PUBLIC) This directory contains the public headers that provide public architecture-specific definitions which can be referenced by both kernel and application code. 2. Split arch_interface.h into "kernel-to-arch interface" and "public arch interface" divisions. - kernel/include/kernel_arch_interface.h * provides private "kernel-to-arch interface" definition. * includes arch/*/include/kernel_arch_func.h to ensure that the interface function implementations are always available. * includes sys/arch_interface.h so that public arch interface definitions are automatically included when including this file. - arch/*/include/kernel_arch_func.h * provides architecture-specific "kernel-to-arch interface" implementation. * only the functions that will be used in kernel and arch source files are defined here. - include/sys/arch_interface.h * provides "public arch interface" definition. * includes include/arch/arch_inlines.h to ensure that the architecture-specific public inline interface function implementations are always available. - include/arch/arch_inlines.h * includes architecture-specific arch_inlines.h in include/arch/*/arch_inline.h. - include/arch/*/arch_inline.h * provides architecture-specific "public arch interface" inline function implementation. * supersedes include/sys/arch_inline.h. 3. Refactor kernel and the existing architecture implementations. - Remove circular dependency of kernel and arch headers. The following general rules should be observed: * Never include any private headers from public headers * Never include kernel_internal.h in kernel_arch_data.h * Always include kernel_arch_data.h from kernel_arch_func.h * Never include kernel.h from kernel_struct.h either directly or indirectly. Only add the kernel structures that must be referenced from public arch headers in this file. - Relocate syscall_handler.h to include/ so it can be used in the public code. This is necessary because many user-mode public codes reference the functions defined in this header. - Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is necessary to provide architecture-specific thread definition for 'struct k_thread' in kernel.h. - Remove any private header dependencies from public headers using the following methods: * If dependency is not required, simply omit * If dependency is required, - Relocate a portion of the required dependencies from the private header to an appropriate public header OR - Relocate the required private header to make it public. This commit supersedes #20047, addresses #19666, and fixes #3056. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-24 23:08:21 +08:00
zephyr_library()
zephyr_library_sources(
cpu_idle.c
fatal.c
window_vectors.S
xtensa: rename files with hyphens to underscores Simply to provide some consistencies on file naming under arch/xtensa. These are all internally used files and are not public. So there is no need to provide a deprecation path for them. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-07 05:42:05 +08:00
xtensa_asm2_util.S
arch: xtensa: Add support for Intel Apollolake Add the necessary architecture changes for Intel Apollolake. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2019-11-19 18:32:32 +08:00
irq_manage.c
xtensa: refactor thread related stuff into its own file... ... from xtensa_asm2.c. Everything has been stuffed inside xtensa_asm2.c where they are all mangled together. So extract thread related stuff into its own file. Note that arch_float_*() may not be thread related but most other architectures put them into thread.c. So we also do it here. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-07 05:55:06 +08:00
thread.c
xtensa: rename xtensa_asm2.c to vector_handlers.c Rename xtensa_asm2.c to have a more meaningful name to actually reflect the content of the file. This file is mostly about handling interrupts and exceptions (via the predefined vectors in Xtensa core). Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-09 05:42:59 +08:00
vector_handlers.c
headers: Refactor kernel and arch headers. This commit refactors kernel and arch headers to establish a boundary between private and public interface headers. The refactoring strategy used in this commit is detailed in the issue This commit introduces the following major changes: 1. Establish a clear boundary between private and public headers by removing "kernel/include" and "arch/*/include" from the global include paths. Ideally, only kernel/ and arch/*/ source files should reference the headers in these directories. If these headers must be used by a component, these include paths shall be manually added to the CMakeLists.txt file of the component. This is intended to discourage applications from including private kernel and arch headers either knowingly and unknowingly. - kernel/include/ (PRIVATE) This directory contains the private headers that provide private kernel definitions which should not be visible outside the kernel and arch source code. All public kernel definitions must be added to an appropriate header located under include/. - arch/*/include/ (PRIVATE) This directory contains the private headers that provide private architecture-specific definitions which should not be visible outside the arch and kernel source code. All public architecture- specific definitions must be added to an appropriate header located under include/arch/*/. - include/ AND include/sys/ (PUBLIC) This directory contains the public headers that provide public kernel definitions which can be referenced by both kernel and application code. - include/arch/*/ (PUBLIC) This directory contains the public headers that provide public architecture-specific definitions which can be referenced by both kernel and application code. 2. Split arch_interface.h into "kernel-to-arch interface" and "public arch interface" divisions. - kernel/include/kernel_arch_interface.h * provides private "kernel-to-arch interface" definition. * includes arch/*/include/kernel_arch_func.h to ensure that the interface function implementations are always available. * includes sys/arch_interface.h so that public arch interface definitions are automatically included when including this file. - arch/*/include/kernel_arch_func.h * provides architecture-specific "kernel-to-arch interface" implementation. * only the functions that will be used in kernel and arch source files are defined here. - include/sys/arch_interface.h * provides "public arch interface" definition. * includes include/arch/arch_inlines.h to ensure that the architecture-specific public inline interface function implementations are always available. - include/arch/arch_inlines.h * includes architecture-specific arch_inlines.h in include/arch/*/arch_inline.h. - include/arch/*/arch_inline.h * provides architecture-specific "public arch interface" inline function implementation. * supersedes include/sys/arch_inline.h. 3. Refactor kernel and the existing architecture implementations. - Remove circular dependency of kernel and arch headers. The following general rules should be observed: * Never include any private headers from public headers * Never include kernel_internal.h in kernel_arch_data.h * Always include kernel_arch_data.h from kernel_arch_func.h * Never include kernel.h from kernel_struct.h either directly or indirectly. Only add the kernel structures that must be referenced from public arch headers in this file. - Relocate syscall_handler.h to include/ so it can be used in the public code. This is necessary because many user-mode public codes reference the functions defined in this header. - Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is necessary to provide architecture-specific thread definition for 'struct k_thread' in kernel.h. - Remove any private header dependencies from public headers using the following methods: * If dependency is not required, simply omit * If dependency is required, - Relocate a portion of the required dependencies from the private header to an appropriate public header OR - Relocate the required private header to make it public. This commit supersedes #20047, addresses #19666, and fixes #3056. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-10-24 23:08:21 +08:00
)
zephyr_library_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
xtensa: add support for thread local storage Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Note that this does not enable TLS for all Xtensa SoC. This is because Xtensa SoCs are highly configurable so that each SoC can be considered a whole architecture. So TLS needs to be enabled on the SoC level, instead of at the arch level. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-10-03 05:55:34 +08:00
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
arch: xtensa: Print backtrace from panic handler This change uses stack frame to print backtrace once exception occurs Printing backtrace helps to identify the cause of exception Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-01-07 14:11:11 +08:00
zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE xtensa_backtrace.c)
zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE debug_helpers_asm.S)
debug: coredump: add xtensa coredump Adds Xtensa as supported architecture for coredump. Fixes a few typos in documentation, Kconfig and a C file. Dumps minimal set of registers shown by 'info registers' in GDB for the sample_controller and ESP32 SOCs. Updates tests. Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2021-10-21 09:53:04 +08:00
zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
arch/xtensa: Add CCOUNT-based timing API Expose the Xtenesa CCOUNT timing register (the lowest level CPU cycle counter) using the arch_timing_*() API. This is the simplest possible way to get this working. Future work might focus on moving the rate configuration into devicetree in a standard way, integrating with the platform clock driver on intel_adsp such that the reported cycle rate tracks runtime changes (though IIRC this is not a SOF requirement), and adding better test coverage to the timing layer, which right now isn't exercised anywhere but in benchmarks. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-06-06 22:49:27 +08:00
zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
xtensa: introduce support for GDB stub This adds basic support for GDB stub on Xtensa. Note that this only provides the common bits on the architecture side. SoC support is also required to fully enable GDB stub on each Xtensa SoC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-27 03:58:21 +08:00
zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
arch/xtensa: Add new MMU layer Andy Ross re-implementation of MMU layer with some subtle changes, like re-using existent macros, fix page table cache property when direct mapping it in TLB. From Andy's original commit message: This is a reworked MMU layer, sitting cleanly below the page table handling in the OS. Notable differences from the original work: + Significantly smaller code and simpler API (just three functions to be called from the OS/userspace/ptable layer). + Big README-MMU document containing my learnings over the process, so hopefully fewer people need to go through this in the future. + No TLB flushing needed. Clean separation of ASIDs, just requires that the upper levels match the ASID to the L1 page table page consistently. + Vector mapping is done with a 4k page and not a 4M page, leading to much more flexibility with hardware memory layout. The original scheme required that the 4M region containing vecbase be mapped virtually to a location other than the hardware address, which makes confusing linkage with call0 and difficult initialization constraints where the exception vectors run at different addresses before and after MMU setup (effectively forcing them to be PIC code). + More provably correct initialization, all MMU changes happen in a single asm block with no memory accesses which would generate a refill. Signed-off-by: Andy Ross <andyross@google.com> Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-11-20 07:44:56 +08:00
zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c)
xtensa: Enable userspace Userspace support for Xtensa architecture using Xtensa MMU. Some considerations: - Syscalls are not inline functions like in other architectures because some compiler issues when using multiple registers to pass parameters to the syscall. So here we have a function call so we can use registers as we need. - TLS is not supported by xcc in xtensa and reading PS register is a privileged instruction. So, we have to use threadptr to know if a thread is an user mode thread. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-12-14 16:35:36 +08:00
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c)
llext: xtensa: add support for local symbol relocations Add support for relocating local symbols, as specified in the .rela.dyn section. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-09-28 19:59:53 +08:00
zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
xtensa: move arch_spin_relax into smp.c arch_spin_relax() does not really fit into the scheme of xtensa_asm2.c as it is mainly about handling interrupts and exceptions. So move it into smp.c, similar to other architectures which arch_spin_relax() defined. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-09 02:09:31 +08:00
zephyr_library_sources_ifdef(CONFIG_SMP smp.c)
xtensa: introduce support for GDB stub This adds basic support for GDB stub on Xtensa. Note that this only provides the common bits on the architecture side. SoC support is also required to fully enable GDB stub on each Xtensa SoC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-27 03:58:21 +08:00
xtensa: add custom mem range check functions This provides custom memory range check functions as it gets a bit complicated with cached/uncached regions. These functions are marked as __weak so SoC or board can override these if needed. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-10-13 02:00:45 +08:00
zephyr_library_sources_ifdef(
CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK
mem_manage.c
)
xtensa: xcc: add a dummy atexit() Some XCC toolchains do not provide atexit() which results in undefined reference error. So add a weak dummy atexit() for this siutation. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-21 08:27:46 +08:00
if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
zephyr_library_sources(xcc_stubs.c)
endif()
Introduce cmake-based rewrite of KBuild Introducing CMake is an important step in a larger effort to make Zephyr easy to use for application developers working on different platforms with different development environment needs. Simplified, this change retains Kconfig as-is, and replaces all Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild offers is replaced by a set of CMake extentions. These extentions have either provided simple one-to-one translations of KBuild features or introduced new concepts that replace KBuild concepts. This is a breaking change for existing test infrastructure and build scripts that are maintained out-of-tree. But for FW itself, no porting should be necessary. For users that just want to continue their work with minimal disruption the following should suffice: Install CMake 3.8.2+ Port any out-of-tree Makefiles to CMake. Learn the absolute minimum about the new command line interface: $ cd samples/hello_world $ mkdir build && cd build $ cmake -DBOARD=nrf52_pca10040 .. $ cd build $ make PR: zephyrproject-rtos#4692 docs: http://docs.zephyrproject.org/getting_started/getting_started.html Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-10-27 21:43:34 +08:00
add_subdirectory(startup)
arch/xtensa: Add special register allocation generator Zephyr likes to use the various Xtensa scratch registers for its own purposes in several places. Unfortunately, owing to the configurability of the architecture, we have to use different registers for different platforms. This has been done so far with a collection of different tricks, some... less elegant than others. Put it all in one place. This is a python script that emites a "zsr.h" header with register assignments for all the existing users. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-09 07:51:04 +08:00
# This produces a preprocessed and regenerated (in the sense of gcc
# -dM, supported by all Xtensa toolchains) core-isa.h file available
# as "core-isa-dM.h". This can be easily parsed by non-C tooling.
#
# Note that this adds the SOC/HAL include directory explicitly, they
arch/xtensa: Fix xcc regression with ZSR Turns out that xt-xcc will bail when faced with a real core-isa.h (it wants you to rely on the builtins in the compiler). Undefine __XCC__ to force it to actually parse and emit declarations for its own header. (Also adds a newline to the generated one-line C file to silence a warning) Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 03:11:08 +08:00
# are the official places where we find core-isa.h. (Also that we
# undefine __XCC_ because that compiler actually trips an error trying
# to build this file to protect against mismatched versions.)
arch/xtensa: Add special register allocation generator Zephyr likes to use the various Xtensa scratch registers for its own purposes in several places. Unfortunately, owing to the configurability of the architecture, we have to use different registers for different platforms. This has been done so far with a collection of different tricks, some... less elegant than others. Put it all in one place. This is a python script that emites a "zsr.h" header with register assignments for all the existing users. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-09 07:51:04 +08:00
set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.h)
set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
arch/xtensa: Fix xcc regression with ZSR Turns out that xt-xcc will bail when faced with a real core-isa.h (it wants you to rely on the builtins in the compiler). Undefine __XCC__ to force it to actually parse and emit declarations for its own header. (Also adds a newline to the generated one-line C file to silence a warning) Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 03:11:08 +08:00
file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
arch/xtensa: Add special register allocation generator Zephyr likes to use the various Xtensa scratch registers for its own purposes in several places. Unfortunately, owing to the configurability of the architecture, we have to use different registers for different platforms. This has been done so far with a collection of different tricks, some... less elegant than others. Put it all in one place. This is a python script that emites a "zsr.h" header with register assignments for all the existing users. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-09 07:51:04 +08:00
add_custom_command(OUTPUT ${CORE_ISA_DM}
arch/xtensa: Fix xcc regression with ZSR Turns out that xt-xcc will bail when faced with a real core-isa.h (it wants you to rely on the builtins in the compiler). Undefine __XCC__ to force it to actually parse and emit declarations for its own header. (Also adds a newline to the generated one-line C file to silence a warning) Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 03:11:08 +08:00
COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
arch/xtensa: Add special register allocation generator Zephyr likes to use the various Xtensa scratch registers for its own purposes in several places. Unfortunately, owing to the configurability of the architecture, we have to use different registers for different platforms. This has been done so far with a collection of different tricks, some... less elegant than others. Put it all in one place. This is a python script that emites a "zsr.h" header with register assignments for all the existing users. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-09 07:51:04 +08:00
-I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
-I${SOC_DIR}/${ARCH}/${SOC_PATH}
${CORE_ISA_IN} -o ${CORE_ISA_DM})
# Generates a list of device-specific scratch register choices
set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zsr.h)
add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
xtensa: mmu: allocate scratch registers for MMU When MMU is enabled, we need some scratch registers to preload page table entries. So update gen_zsr.py to that. Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-02-17 03:25:48 +08:00
$<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
arch/xtensa: Add special register allocation generator Zephyr likes to use the various Xtensa scratch registers for its own purposes in several places. Unfortunately, owing to the configurability of the architecture, we have to use different registers for different platforms. This has been done so far with a collection of different tricks, some... less elegant than others. Put it all in one place. This is a python script that emites a "zsr.h" header with register assignments for all the existing users. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-09 07:51:04 +08:00
${CORE_ISA_DM} ${ZSR_H})
add_custom_target(zsr_h DEPENDS ${ZSR_H})
add_dependencies(zephyr_interface zsr_h)