183 lines
5.1 KiB
C
183 lines
5.1 KiB
C
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_
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#include <sys/util.h>
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#define DAIFSET_FIQ BIT(0)
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#define DAIFSET_IRQ BIT(1)
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#define DAIFSET_ABT BIT(2)
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#define DAIFSET_DBG BIT(3)
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#define DAIF_FIQ BIT(6)
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#define DAIF_IRQ BIT(7)
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#define DAIF_ABT BIT(8)
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#define DAIF_DBG BIT(9)
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#define DAIF_MASK (0xf << 6)
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#define SPSR_MODE_EL0T (0x0)
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#define SPSR_MODE_EL1T (0x4)
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#define SPSR_MODE_EL1H (0x5)
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#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(20) | BIT(11))
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#define SCTLR_M BIT(0)
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#define SCTLR_A BIT(1)
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#define SCTLR_C BIT(2)
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#define SCTLR_SA BIT(3)
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#define SCTLR_I BIT(12)
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#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
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#define SCR_EL3_NS BIT(0)
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#define SCR_EL3_IRQ BIT(1)
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#define SCR_EL3_FIQ BIT(2)
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#define SCR_EL3_EA BIT(3)
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#define SCR_EL3_RW BIT(10)
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/*
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* TODO: ACTLR is of class implementation defined. All core implementations
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* in armv8a have the same implementation so far w.r.t few controls.
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* When there will be differences we have to create core specific headers.
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*/
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#define ACTLR_EL3_CPUACTLR BIT(0)
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#define ACTLR_EL3_CPUECTLR BIT(1)
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#define ACTLR_EL3_L2CTLR BIT(4)
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#define ACTLR_EL3_L2ECTLR BIT(5)
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#define ACTLR_EL3_L2ACTLR BIT(6)
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#define CPTR_EL3_RES_VAL (0x0)
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#define CPTR_EL3_EZ BIT(8)
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#define CPTR_EL3_TFP BIT(9)
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#define CPTR_EL3_TTA BIT(20)
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#define CPTR_EL3_TCPAC BIT(31)
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#define HCR_EL2_FMO BIT(3)
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#define HCR_EL2_IMO BIT(4)
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#define HCR_EL2_AMO BIT(5)
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#define SPSR_EL3_h BIT(0)
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#define SPSR_EL3_TO_EL1 (0x2 << 1)
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/* System register interface to GICv3 */
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICC_SGI1R S3_0_C12_C11_5
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_RPR_EL1 S3_0_C12_C11_3
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#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
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#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
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#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
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#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
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#define ICC_IAR0_EL1 S3_0_C12_C8_0
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#define ICC_IAR1_EL1 S3_0_C12_C12_0
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#define ICC_EOIR0_EL1 S3_0_C12_C8_1
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#define ICC_EOIR1_EL1 S3_0_C12_C12_1
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#define ICC_SGI0R_EL1 S3_0_C12_C11_7
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/* register constants */
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#define ICC_SRE_ELx_SRE BIT(0)
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#define ICC_SRE_ELx_DFB BIT(1)
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#define ICC_SRE_ELx_DIB BIT(2)
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#define ICC_SRE_EL3_EN BIT(3)
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/* ICC SGI macros */
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#define SGIR_TGT_MASK 0xffff
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#define SGIR_AFF1_SHIFT 16
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#define SGIR_INTID_SHIFT 24
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#define SGIR_INTID_MASK 0xf
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#define SGIR_AFF2_SHIFT 32
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#define SGIR_IRM_SHIFT 40
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#define SGIR_IRM_MASK 0x1
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#define SGIR_AFF3_SHIFT 48
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#define SGIR_AFF_MASK 0xf
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#define SGIR_IRM_TO_AFF 0
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#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
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((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
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(((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
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(((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
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(((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
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(((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
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((_tgt) & SGIR_TGT_MASK))
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/* Implementation defined register definations */
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#if defined(CONFIG_CPU_CORTEX_A72)
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#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT 5
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT 9
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 2
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK 7
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#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE 1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 2
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK 7
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#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE 1
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#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (1 << 6)
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#endif /* CONFIG_CPU_CORTEX_A72 */
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#ifndef _ASMLANGUAGE
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/* Core sysreg macros */
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#define read_sysreg(reg) ({ \
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uint64_t val; \
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__asm__ volatile("mrs %0, " STRINGIFY(reg) : "=r" (val));\
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val; \
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})
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#define write_sysreg(val, reg) ({ \
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__asm__ volatile("msr " STRINGIFY(reg) ", %0" : : "r" (val));\
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})
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#endif /* !_ASMLANGUAGE */
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL3 (0x3)
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#define MODE_EL2 (0x2)
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#define MODE_EL1 (0x1)
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#define MODE_EL0 (0x0)
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#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
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#define ESR_EC(esr) (((esr) >> 26) & BIT_MASK(6))
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#define ESR_IL(esr) (((esr) >> 25) & BIT_MASK(1))
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#define ESR_ISS(esr) ((esr) & BIT_MASK(25))
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/* mpidr */
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFF3_SHIFT 32
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#define MPIDR_AFFLVL(mpidr, aff_level) \
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(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
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#define GET_MPIDR() read_sysreg(mpidr_el1)
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#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_ */
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