zephyr/include/arch
Kumar Gala 1badf77961 arch: arm: aarch32: Fix syscall inline asm
The inline asm code was not conveying in all cases that registers r1-r3
would get clobbered by the SVC handler code.  In the cases that we can't
list r1-r3 in the clobber list the registers need to show up as outputs
to know that they values are not preserved by the callee.

Fixes #30393

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-01-20 17:02:14 +01:00
..
arc tests: coverage: exclude the CODE UNREACHABLE of code coverage 2021-01-15 12:42:00 -05:00
arm arch: arm: aarch32: Fix syscall inline asm 2021-01-20 17:02:14 +01:00
common
nios2
posix
riscv tests: coverage: exclude the CODE UNREACHABLE of code coverage 2021-01-15 12:42:00 -05:00
sparc sparc: add support for thread local storage 2020-11-13 14:53:55 -08:00
x86 tests: coverage: exclude the CODE UNREACHABLE of code coverage 2021-01-15 12:42:00 -05:00
xtensa xtensa: remove core-macros.h from xtensa HAL 2021-01-14 09:40:08 -05:00
arch_inlines.h
cpu.h arch: Add SPARC processor architecture 2020-11-13 14:53:55 -08:00
syscall.h arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00