128 lines
3.5 KiB
C
128 lines
3.5 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM AArch32 public exception handling
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*
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* ARM AArch32-specific kernel exception handling interface. Included by
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* arm/arch.h.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <devicetree.h>
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#include <arch/arm/aarch32/cortex_m/nvic.h>
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/* for assembler, only works with constants */
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#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
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/*
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* In architecture variants with non-programmable fault exceptions
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* (e.g. Cortex-M Baseline variants), hardware ensures processor faults
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* are given the highest interrupt priority level. SVCalls are assigned
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* the highest configurable priority level (level 0); note, however, that
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* this interrupt level may be shared with HW interrupts.
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*
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* In Cortex variants with programmable fault exception priorities we
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* assign the highest interrupt priority level (level 0) to processor faults
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* with configurable priority.
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* The highest priority level may be shared with either Zero-Latency IRQs (if
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* support for the feature is enabled) or with SVCall priority level.
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* Regular HW IRQs are always assigned priority levels lower than the priority
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* levels for SVCalls, Zero-Latency IRQs and processor faults.
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*
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* PendSV IRQ (which is used in Cortex-M variants to implement thread
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* context-switching) is assigned the lowest IRQ priority level.
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*/
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#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
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#define _EXCEPTION_RESERVED_PRIO 1
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#else
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#define _EXCEPTION_RESERVED_PRIO 0
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#endif
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#define _EXC_FAULT_PRIO 0
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#ifdef CONFIG_ZERO_LATENCY_IRQS
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#define _EXC_ZERO_LATENCY_IRQS_PRIO 0
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#define _EXC_SVC_PRIO 1
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#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + 1)
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#else
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#define _EXC_SVC_PRIO 0
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#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO)
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#endif
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#define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
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/* Use lowest possible priority level for PendSV */
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#define _EXC_PENDSV_PRIO 0xff
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#define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO)
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#endif /* CONFIG_CPU_CORTEX_M */
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#ifdef _ASMLANGUAGE
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GTEXT(z_arm_exc_exit);
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#else
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Additional register state that is not stacked by hardware on exception
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* entry.
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*
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* These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error().
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* When information for a member is unavailable, the field is set to zero.
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*/
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info {
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_callee_saved_t *callee;
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uint32_t msp;
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uint32_t exc_return;
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};
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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struct __esf {
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struct __basic_sf {
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sys_define_gpr_with_alias(a1, r0);
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sys_define_gpr_with_alias(a2, r1);
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sys_define_gpr_with_alias(a3, r2);
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sys_define_gpr_with_alias(a4, r3);
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sys_define_gpr_with_alias(ip, r12);
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sys_define_gpr_with_alias(lr, r14);
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sys_define_gpr_with_alias(pc, r15);
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uint32_t xpsr;
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} basic;
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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float s[16];
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uint32_t fpscr;
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uint32_t undefined;
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#endif
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info extra_info;
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#endif
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};
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extern uint32_t z_arm_coredump_fault_sp;
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typedef struct __esf z_arch_esf_t;
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#ifdef CONFIG_CPU_CORTEX_M
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extern void z_arm_exc_exit(void);
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#else
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extern void z_arm_exc_exit(bool fatal);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ */
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