152 lines
2.9 KiB
INI
152 lines
2.9 KiB
INI
# Copyright 2018 NXP
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# SPDX-License-Identifier: BSD-3-Clause
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set _WORKAREASIZE 0x2000
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adapter_khz 1000
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interface jlink
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transport select jtag
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set _WORKAREASIZE 0x1000
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set _CHIPNAME rv32m1
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reset_config srst_only
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# OpenCores Mohor JTAG TAP ID
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set _CPUTAPID 0x249511C3
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
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# Select the TAP core we are using
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tap_select mohor
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# Select the debug unit core we are using. This debug unit as an option.
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set ADBG_USE_HISPEED 1
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# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
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# on burst reads and writes to improve download speeds.
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# This option must match the RTL configured option.
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du_select adv [expr $ADBG_USE_HISPEED]
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# Select core 0
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core_select 0
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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$_TARGETNAME configure -event gdb-detach {
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resume
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}
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
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flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
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proc ri5cy_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFF03FF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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proc cm4_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFFFFFF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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proc zero_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFF03BF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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proc cm0_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFFFFBF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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# All cores are available, CM4 & RI5CY boot first
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proc core0_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFFA3FF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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# All cores are available, CM0 & ZERO_RISCY boot first
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proc core1_boot { } {
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# Erase all blok unsecure
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mwb 0x40023000 0x70
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mww 0x40023004 0x49000000
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mwb 0x40023000 0x80
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sleep 1000
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mwb 0x40023000 0x70
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mww 0x40023008 0xFFFFA3BF
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mww 0x40023004 0x43840000
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mwb 0x40023000 0x80
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sleep 2
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}
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