cf1d374276
Introduces a new rv32m1_vega board configuration for the zero-riscy core. It assumes that the soc has been reconfigured with openocd to boot to the zero-riscy core instead of the ri5cy core. Refactors the board-level device tree so the ri5cy and zero-riscy configurations share common definitions for the led, button, and sensor nodes. Tested with: - samples/hello_world - samples/synchronization - samples/basic/blinky - samples/basic/button - samples/sensor/fxos8700 Signed-off-by: Maureen Helm <maureen.helm@nxp.com> |
||
---|---|---|
.. | ||
hifive1 | ||
m2gl025_miv | ||
qemu_riscv32 | ||
rv32m1_vega | ||
index.rst |