Yong Cong Sin 4e54cff223 soc: qemu: riscv: update IRQ config ... - Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the devicetree - Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to be able to encode the L2 IRQs. - Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024) Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase accordingly, so that it won't overflow the configured bits. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>		2024-09-06 14:06:23 -05:00
..
malta	…
virt_riscv	soc: qemu: riscv: update IRQ config	2024-09-06 14:06:23 -05:00