soc: qemu: riscv: update IRQ config

- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
  devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
  be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)

Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>

soc/qemu/virt_riscv/Kconfig.defconfig

@@ -19,11 +19,14 @@ config 2ND_LVL_ISR_TBL_OFFSET
 config 2ND_LVL_INTR_00_OFFSET
 	default 11
 
+config 2ND_LEVEL_INTERRUPT_BITS
+	default 11
+
 config MAX_IRQ_PER_AGGREGATOR
-	default 52
+	default 1024
 
 config NUM_IRQS
-	default 1035
+	default 1036
 
 config PMP_SLOTS
 	default 16

tests/drivers/build_all/interrupt_controller/intc_plic/testcase.yaml

@@ -21,6 +21,7 @@ tests:
       DTC_OVERLAY_FILE="./app.multi_instance.overlay"
     extra_configs:
       - CONFIG_NUM_IRQS=116
+      - CONFIG_MAX_IRQ_PER_AGGREGATOR=52
       - CONFIG_MULTI_LEVEL_INTERRUPTS=y
       - CONFIG_DYNAMIC_INTERRUPTS=y
       - CONFIG_NUM_2ND_LEVEL_AGGREGATORS=2

tests/kernel/gen_isr_table/testcase.yaml

@@ -85,12 +85,14 @@ tests:
     platform_allow: qemu_riscv32
     filter: CONFIG_RISCV_PRIVILEGED
     extra_configs:
+      - CONFIG_MAX_IRQ_PER_AGGREGATOR=52
       - CONFIG_1ST_LEVEL_INTERRUPT_BITS=7
       - CONFIG_2ND_LEVEL_INTERRUPT_BITS=9
   arch.interrupt.gen_isr_table.bit_shift_3rd_level:
     platform_allow: qemu_riscv32
     filter: CONFIG_RISCV_PRIVILEGED
     extra_configs:
+      - CONFIG_MAX_IRQ_PER_AGGREGATOR=52
       - CONFIG_MULTI_LEVEL_INTERRUPTS=y
       - CONFIG_2ND_LEVEL_INTERRUPTS=y
       - CONFIG_3RD_LEVEL_INTERRUPTS=y